4.6.3 Configuration Protection

Once the device has been configured, writes to register bit fields by the host controller are typically no longer necessary. However, should the host controller encounter a fault, it is possible that incorrect firmware execution may result in errant writes to critical registers resulting in misconfiguration that could interfere with system-wide communication among other nodes on the bus. For this reason, the LAN8650/1 includes a feature to prevent writes to critical registers once configuration by the host controller is complete.

The Write Enable (WREN) bit in the Configuration Protection Control (CFGPRTCTL) register enables and disables (blocks) writes to all integrated PHY registers in MMS2 (PHY PCS Registers), MMS3 (PHY PMA/PMD Registers), and MMS4 (PHY Vendor Specific Registers) as well as non-PHY registers identified in Table 4-6. Following reset, the Write Enable bit is set indicating that configuration protection is inactive and writing to all register bit fields is enabled. Once the host controller has configured the device , it may write a ‘0’ to the Write Enable bit to activate configuration protection and disable writing to all PHY configuration register bit fields preventing changes to the configuration. When register configuration protection is active, All integrated PHY and non-PHY registers not listed in the table below may be written.

By default, the Configuration Protection Control register is locked and the Write Enable bit cannot be modified. Changing the Write Enable bit requires the Configuration Protection Control register to be unlocked. Unlocking the Configuration Protection Control register requires writing two unique key values in sequence to the Configuration Protection Control register. The host controller must first write a value of 53464352h to the Configuration Protection Control register. Once written, the Key #1 Accepted (KEY1) status bit will be set. The host controller must then write a value of 434F4E46h to the Configuration Protection Control register resulting in the Key #2 Accepted (KEY2) status bit being set. If any value other than 434F4E46h is written after the first key value has been accepted, the LOCKED state is re-entered, the Key #1 Accepted status bit will be cleared and the unlocking process must be restarted. Additionally, writing to any register other than the Configuration Protection Control will also result in the register being locked again with the Key #1 Accepted status bit cleared. When both key values have been written in the correct sequence and accepted as indicated by both the KEY1 Accepted and KEY2 Accepted status bits being set, the Configuration Protection Control register is unlocked and the host controller may then write and modify the Write Enable bit, enabling or disabling writes to all register bit fields. When the Configuration Protection Control register is unlocked, a write to any other register will cause the Configuration Protection Control register to immediately become locked again. See Figure 4-11.