31.3.3.4 Output Formats

The resolution of an ADC output is given by the number of bits used in the conversion:

An 8-bit ADC means 256 discrete levels (from 0 to 255)
A 10-bit ADC means 1024 discrete levels (from 0 to 1023)

A single-ended conversion measures the voltage difference between one input voltage and ground. The result of an N-bit single-ended conversion is an unsigned (positive) integer between 0 and the maximum value 2^N - 1:

ADC result ϵ [0, 2^N-1]

The output from an ADC conversion is given by the equations below:


Equation	Explanation
Single-Ended 8-bit conversion:
$R E S U L T = \frac{V_{I N}}{V_{R E F}} \times 255$	The multiplication factor is 255 (2⁸ - 1 = 255) The result (RES) will be an integer between 0 and 255
Single-Ended 10-bit conversion:
$R E S U L T = \frac{V_{I N}}{V_{R E F}} \times 1023$	The multiplication factor is 1023 (2¹⁰ - 1 = 1023) The result (RES) will be an integer between 0 and 1023

Explanation to the equations:

V_IN is the input voltage
V_REF is the selected reference voltage

The ADC has two output registers, the Sample (ADCn.SAMPLE) and Result (ADCn.RESULT) registers. The 16-bit Sample register will always be updated with the latest ADC conversion output (one sample). In Series and Burst accumulation mode, samples are added in an internal sample accumulator, which is configured by the Sample Accumulation Number Select (SAMPNUM) bit field in the Control F (ADCn.CTRLF) register. The accumulated result will automatically transferred to the 16-bit Result register when all samples are completed. When accumulating more than 64 samples, only the 16 MSBs of the accumulated result will be available in the Result register. In single conversion modes, the Result register will be updated with the latest sample, identical to the Sample register.

The Result Scaling (SCALING) bit field in the Control F (ADCn.CTRLF) register enables the left-shifting of the output data. If enabled, this will left-shift the output in both the Result and Sample registers. Left-adjusting the result will effectively scale the result such that however many samples are accumulated, the MSb of the result is always positioned at the leftmost bit position in the Result register.

The Result Scaling (SCALING) bit field in the Control F (ADCn.CTRLF) register determines how data is presented in the SAMPLE and RESULT registers, as shown in the following table.

Table 31-2. Scaling
SCALING bit field value	Description	SAMPLE	RESULT
0x0	None	LSb at bit 0	Accumulated value with LSb at bit 0
0x1	Left Adjust	MSb at bit 15	Accumulated value scaled corresponding to number of samples. Up to 16 bits available with MSb at bit 15.
0x2	Average	LSb at bit 0	Accumulated value divided by the number of samples, with LSb at bit 0

The data format for a sample is an unsigned number, where 0x000 represents zero and 0x3FF represents the largest number (full scale). If the analog input is higher than the reference level of the ADC, the 10-bit ADC output will be equal to the maximum value of 0x3FF. Likewise, if the input is below 0V, the ADC output will be 0x000.

The following table shows the Result register output formats by mode of operation and left adjustment.

Table 31-3. RESULT Register
MODE⁽¹⁾	SCALING	RESULT[15:10]	RESULT[9:8]	RESULT[7:0]
`0`	X⁽²⁾	`0x00`		Conversion[9:2]
`1`	0, 2	`0x00`	Conversion[9:0]
`1`	1	Conversion[9:0] << 6
`2`, `3`	0⁽³⁾	Accumulation[15:0]
	1⁽³⁾	Left Adjusted Accumulation[15:0]
	2	`0x00`	Averaged Accumulation[9:0]

Note:

See the Operation Modes section.
Left adjustment is not available in 8-bit mode.
When accumulating more than 64 samples (SAMPNUM > 6), only the 16 MSBs of the accumulated result will be available in the Result register, regardless of the value of the Result Scaling (SCALING) bit in the Control F (ADCn.CTRLF) register.

The following table shows the Sample register output formats by mode of operation and left adjustment.

Table 31-4. SAMPLE Register
MODE⁽¹⁾	SCALING	SAMPLE[15:10]	SAMPLE[9:8]	SAMPLE[7:0]
`0`	X	`0x00`		Conversion[9:2]
`Other`	0, 2	`0x00`	Conversion[9:0]
`Other`	1	Conversion[9:0] << 6

Note:

See the Operation Modes section.