22.5.1 Control A


Bit	7	6	5	4	3	2	1	0
		RUNSTDBY	CASCADE	SYNCUPD	CLKSEL[2:0]			ENABLE
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0

Bit 6 – RUNSTDBY Run Standby

Writing a ‘1’ to this bit enables the TCB peripheral to run in the Standby sleep mode.

Bit 5 – CASCADE Cascade Two Timer/Counters

Writing a ‘1’ to this bit enables cascading two 16-bit Timer/Counters type B (TCBn) for 32-bit operation using the Event System. This bit must be ‘1’ for the TCBn used for the two Most Significant Bytes (MSBs). When this bit is ‘1’, the selected event source for capture (CAPT) is delayed by one peripheral clock cycle, compensating for the carry propagation delay when cascading two counters via the Event System.

Bit 4 – SYNCUPD Synchronize Update

When this bit is written to ‘1’, the TCBn restarts whenever TCEn is restarted or overflows, which can synchronize the capture with the PWM period. If TCEn is selected as the clock source, the TCB will restart when that TCEn is restarted. For other clock selections, it will restart together with TCEn.

Bits 3:1 – CLKSEL[2:0] Clock Select

Writing this bit field selects the clock source for this peripheral.


Value	Name	Description
`0x0`	DIV1	CLK_PER
`0x1`	DIV2	CLK_PER/2
`0x2`	DIV8	CLK_PER/8
`0x3`	DIV64	CLK_PER/64
`0x4`	DIV1024	CLK_PER/1024
`0x5`	TCE0	CLK_TCE from TCE0
`0x6`	-	Reserved
`0x7`	EVENT	Positive edge on event input

Bit 0 – ENABLE Enable

Writing a ‘1’ to this bit enables the TCB peripheral.

Name:	CTRLA
Offset:	0x00
Reset:	0x00
Property:	-