10.2 Interrupt Vector Mapping

Each interrupt vector is connected to one peripheral instance, as shown in the table below. A peripheral can have one or more interrupt sources. For more details about the available interrupt sources, see the Interrupt section in the Functional Description of the respective peripheral.

An interrupt flag is set in the interrupt flag (<peripheral>.INTFLAGS) register of the peripheral when the interrupt condition occurs, even if the interrupt is not enabled.

An interrupt is enabled or disabled by writing to the corresponding Interrupt Enable bit in the peripheral's Interrupt Control (<peripheral>.INTCTRL) register.

An interrupt request is generated when the corresponding interrupt is enabled and the interrupt flag is set. The interrupt request remains active until the interrupt flag is cleared. For details on how to clear interrupt flags, see the peripheral’s interrupt flag (<peripheral>.INTFLAGS) register.

Note: Interrupts must be enabled globally for interrupt requests to be generated.

Table 10-3. Interrupt Vector Mapping
Vector Number	Program Address (Word)	Interrupt Vector (Name)	Interrupt Source (Name)	Description	14-Pin	20-Pin	28-Pin	32-Pin
0	0x00	RESET	-	Device Reset interrupt	X	X	X	X
1	0x02	NMI	OPC	Non-Maskable Illegal Opcode interrupt from CPU	X	X	X	X
			SPLIM	Non-Maskable Stack Pointer Limit interrupt from CPU	X	X	X	X
			ERROR	Non-Maskable interrupt available for CRCSCAN	X	X	X	X
2	0x04	BOD_VLM	VLM	Voltage Level Monitoring interrupt from BOD	X	X	X	X
3	0x06	CRCSCAN_INT	DONE	Scan Done interrupt from CRCSCAN	X	X	X	X
3	0x06	CRCSCAN_INT	PERIOD	Scan Period Done interrupt from CRCSCAN	X	X	X	X
4	0x08	RTC_CNT	CMP	Compare interrupt from RTC	X	X	X	X
4	0x08	RTC_CNT	OVF	Overflow interrupt from RTC	X	X	X	X
5	0x0A	RTC_PIT	PIT	Periodic Interrupt Timer interrupt from RTC	X	X	X	X
6	0x0C	CCL_CCL	LUTn	LUTn interrupt from CCL	X	X	X	X
7	0x0E	PORTA_PORT	PAn	Pin n interrupt from PORTA	X	X	X	X
8	0x10	TCE0_OVF	OVF	Overflow interrupt from TCE0	X	X	X	X
9	0x12	TCE0_CMP0	CMP0	Compare 0 interrupt from TCE0	X	X	X	X
10	0x14	TCE0_CMP1	CMP1	Compare 1 interrupt from TCE0	X	X	X	X
11	0x16	TCE0_CMP2	CMP2	Compare 2 interrupt from TCE0	X	X	X	X
12	0x18	TCB0_INT	CAPT	Capture interrupt from TCB0	X	X	X	X
12	0x18	TCB0_INT	OVF	Overflow interrupt from TCB0	X	X	X	X
13	0x1A	TCB1_INT	CAPT	Capture interrupt from TCB1	X	X	X	X
13	0x1A	TCB1_INT	OVF	Overflow interrupt from TCB1	X	X	X	X
14	0x1C	TWI0_TWIC	DIF	Client Data Transmit or Receive Complete interrupt from TWI0 in Client mode	X	X	X	X
14	0x1C	TWI0_TWIC	APIF	Client Address or Stop interrupt from TWI0 in Client mode	X	X	X	X
15	0x1E	TWI0_TWIH	RIF	Host Read Complete interrupt from TWI0 in Host mode	X	X	X	X
15	0x1E	TWI0_TWIH	WIF	Host Write Complete interrupt from TWI0 in Host mode	X	X	X	X
16	0x20	SPI0_INT	RXC	Receive Complete interrupt from SPI0 in Buffered mode	X	X	X	X
			TXC	Transmit Complete interrupt from SPI0 in Buffered mode	X	X	X	X
			DRE	Data Register Empty interrupt from SPI0 in Buffered mode	X	X	X	X
			SS	Slave Select interrupt from SPI0 in Buffered mode	X	X	X	X
			IF	Transmit Complete interrupt from SPI0 in Normal mode	X	X	X	X
			WRCOL	Write Collision interrupt from SPI0 in Normal mode	X	X	X	X
17	0x22	USART0_ERR	ISF	Auto-Baud Error/Invalid Sync Field interrupt from USART0	X	X	X	X
			PERR	Parity Error interrupt from USART0	X	X	X	X
			FERR	Frame Error interrupt from USART0	X	X	X	X
			BUFOVF	Buffer Overflow interrupt from USART0	X	X	X	X
			COLL	Transmit Collision Detection interrupt from USART0	X	X	X	X
18	0x24	USART0_RXC	RXC	Receive Complete interrupt from USART0	X	X	X	X
			RXS	Receive Start-of-Frame interrupt from USART0	X	X	X	X
			RXBRK	Receive Valid Break and Synchronization interrupt from USART0	X	X	X	X
19	0x26	USART0_DRE	DRE	Data Register Empty interrupt from USART0	X	X	X	X
19	0x26	USART0_DRE	CTSIC	Clear to Send Input Change interrupt from USART0	X	X	X	X
20	0x28	USART0_TXC	TXC	Transmit Complete interrupt from USART0	X	X	X	X
21	0x2A	PORTD_PORT	PDn	Pin n interrupt from PORTD	X	X	X	X
22	0x2C	AC0_AC	CMP	Compare interrupt from AC0	X	X	X	X
23	0x2E	ADC0_ERROR	TRIGOVR	Trigger Overrun interrupt from ADC0	X	X	X	X
			SAMPOVR	Sample Overwrite interrupt from ADC0	X	X	X	X
			RESOVR	Result Overwrite interrupt from ADC0	X	X	X	X
24	0x30	ADC0_RESRDY	RESRDY	Result Ready interrupt from ADC0	X	X	X	X
24	0x30	ADC0_RESRDY	WCMP	Window Compare interrupt from ADC0	X	X	X	X
25	0x32	ADC0_SAMPRDY	SAMPRDY	Sample Ready interrupt from ADC0	X	X	X	X
25	0x32	ADC0_SAMPRDY	WCMP	Window Compare interrupt from ADC0	X	X	X	X
26	0x34	PORTC_PORT	PCn	Pin n interrupt from PORTC	X	X	X	X
27	0x36	PORTF_PORT	PFn	Pin n interrupt from PORTF	X	X	X	X
28	0x38	NVMCTRL_NVMREADY	EEREADY	EEPROM Ready interrupt	X	X	X	X
28	0x38	NVMCTRL_NVMREADY	FLREADY	Flash Ready interrupt	X	X	X	X