7.1.4 Timing Descriptions

I²C Host Read Bit Timing

Host read is to receive gesture reports and command responses from the MXG3141. The timing diagram is shown below:

• Address bits are latched into the MXG3141 on the rising edges of SCL.
• Data bits are latched out of the MXG3141 on the rising edges of SCL.
• ACK bit:
  • MXG3141 presents the ACK bit on the ninth clock for address acknowledgment
  • I²C host presents the ACK bit on the ninth clock for data acknowledgment
• The I²C host must monitor the SCL pin prior to asserting another clock pulse, as the MXG3141 may be holding off the I²C host by stretching the clock.

I²C Communication Steps

1. SCL and SDA lines are Idle high.
2. I²C host presents Start bit to the MXG3141 by taking SDA high-to-low, followed by taking SCL high-to-low.
3. I²C host presents 7-bit address, followed by a R/W = 1 (Read mode) bit to the MXG3141 on SDA, at the rising edge of eight host clock (SCL) cycles.
4. MXG3141 compares the received address to its Device ID. If they match, the MXG3141 acknowledges (ACK) the host sent address by presenting a low on SDA, followed by a low-high-low on SCL.
5. MXG3141 host monitors SCL, as the MXG3141 may be clock-stretching, holding SCL low to indicate that the I²C host should wait.
6. I²C host receives eight data bits (MSB first) presented on SDA by the MXG3141, at eight sequential I²C host clock (SCL) cycles. The data is latched out on SCL falling edges to ensure it is valid during the subsequent SCL high time.
7. If data transfer is not complete, then:
   • I²C host acknowledges (ACK) reception of the eight data bits by presenting a low on SDA, followed by a low-high-low on SCL.
   • Go to Step 5.
8. If data transfer is complete, then:
   • I²C host NACK’s reception of the eight data bits and a completed data transfer by presenting a high on SDA, followed by a low-high-low on SCL.

I²C Host Write Bit Timing

I²C host write is to send supported commands to the MXG3141. The timing diagram is shown below:

• Address bits are latched into the MXG3141 on the rising edges of SCL.
• Data bits are latched into the MXG3141 on the rising edges of SCL.
• ACK bit:
  • MXG3141 presents the ACK bit on the ninth clock for address acknowledgment
  • MXG3141 presents the ACK bit on the ninth clock for data acknowledgment
• The host must monitor the SCL pin prior to asserting another clock pulse, as the MXG3141 may be holding off the host by stretching the clock.

I²C Communication Steps

1. SCL and SDA lines are Idle high.
2. I²C host presents Start bit to the MXG3141 by taking SDA high-to-low, followed by taking SCL high-to-low.
3. I²C host presents 7-bit address, followed by a R/W = 0 (Write mode) bit to the MXG3141 on SDA, at the rising edge of eight host clock (SCL) cycles.
4. MXG3141 compares the received address to its Device ID. If they match, the MXG3141 acknowledges (ACK) the I²C host sent address by presenting a low on SDA, followed by a low-high-low on SCL.
5. I²C host monitors SCL, as the MXG3141 may be clock stretching, holding SCL low to indicate the I²C host should wait.
6. I²C host presents eight data bits (MSB first) to the MXG3141 on SDA, at the rising edge of eight host clock (SCL) cycles.
7. MXG3141 acknowledges (ACK) receipt of the eight data bits by presenting a low on SDA, followed by a low-high-low on SCL.
8. If data transfer is not complete, then go to Step 5.
9. Host presents a Stop bit to the MXG3141 by taking SCL low-high, followed by taking SDA low-to-high.