2.1.3.2 Async Assert, Sync De-assert

Async Assert, Sync De-assert has asynchronous assertion and synchronus de-assertion of reset to CLK_50MHZ.

When you select asynchronous reset, the following warning message is shown:

Warning: When selecting the Asynchronous Assertion, Synchronous De - assertion reset type, it is recommended to use an SET mitigated approach when connecting an async reset signal to the PLL_RST_N input of this core. An external reset can enter the device using a CLKBUF macro on a GB# pin, or an RGRESET macro can be manually instantiated and connected to a triplicated internal logic cone. For more information, refer to App Note AC463.

Libero® SoC v2022.2

2.1.3.2 Async Assert, Sync De-assert