2.4.1.2 Gated Clock Configuration

For GL[x]/Y[x], Clock Gating is an inherent feature for RTG4 CCC. The GL[x]_Y[x]_EN signal gates both the global network driven by the GL[x] and the fabric local routing resource driven by Y[x], where x can be 0, 1, 2, or 3.

Slow GL or Y's must be enabled before the other GL or Y's are enabled, as the lock CCC_[0/1]_LOCK is dependent on the slow [GL/Y] frequency.