5 Stack-Up Design

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A good stack-up design leads to better performance. The number of layers in the stack-up depends on the following factors:

The board's form factor
The number of signals to be routed
Power requirements

Based on these factors, the designer chooses how many layers the board requires.

The upper-power layers must be used for high-priority supplies. High-switching current supplies should be placed vertically close to the devices to decrease the distance that the current needs to travel through the vias. Ground planes should be placed adjacent to the high-transient current power planes to reduce inductance and to provide decoupling of higher frequency noise.

It is good to have power and ground layers side-by-side so that the inter-plane capacitance provides better decoupling at high frequencies. The effect of vias on power pins is reduced by placing a power plane near the device. Signal integrity depends on how well the traces have controlled impedance, so it is always recommended to have controlled impedance.

Tip: Microchip recommends that all critical high-speed signals, such as DDR and transceiver PCIe signals, have a solid ground reference. These signals should be separated from each other by a good distance, ground, or power planes. This minimizes crosstalk and provides balanced and clean transmission lines with properly controlled characteristic impedance between devices and other board components. For the best performance, use dedicated ground plane layers that are continuous across the entire board area. Power planes can provide an adequate reference; however, the power planes should be related to the signals they serve to reference.

Important: Do not use unrelated power planes as a signal reference.

Slots should not interrupt the planes, or else they can force current to find an alternate return path. This undesired return path may cause a localized bounce on the power or ground plane that can be capacitively coupled to all signals adjacent to the planes

For example, the FC484 1.0 mm package features a single-trace breakout. The layers required for FC484 package are the following:

Signal layers: 4
Power plane: 2
Ground layer: 4

Table 5-1. Sample Stack-Up Layers
Layer No.	Via	Description	Layer Name	Material Type	Dielectric Constant	Dielectric Thickness	Copper Thickness
		Solderm...		Dielectric	3.3	0.5
1	8	Signal	Top/Signal	Conductive			1.4
		Prepreg		Dielectric	4.3	3
2		Plane	GND	Conductive			1.4
		Core		Dielectric	4.3	5
3		Signal	Signal Layer	Conductive			1.4
		Prepreg		Dielectric	4.3	5
4		Signal	GND	Conductive			1.4
		Core		Dielectric	4.3	5
5		Plane	VDD/Power Supply	Conductive			1.4
		Prepreg		Dielectric	4.3	18
6		Plane	VDD/Power Supply	Conductive			1.4
		Core		Dielectric	4.3	5
7		Signal	GND	Conductive			1.4
		Prepreg		Dielectric	4.3	5
8		Signal	Signal Layer	Conductive			1.4
		Core		Dielectric	4.3	5
9		Plane	Ground	Conductive			1.4
		Prepreg		Dielectric	4.3	3
10		Signal	Bottom/Signal	Conductive			1.4
		Solderm...		Dielectric	3.3	0.5

AN5672

5 Stack-Up Design