29.7.14 Parallel Programming Characteristics

Note: 1. The timing requirements shown in the first figure in this section (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply to loading operation.

Note: 1. The timing requirements shown in the first figure in this section (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply to reading operation.

Table 29-12. Parallel Programming Characteristics, VCC = 5V ± 10%
Symbol	Parameter	Min	Max	Units
V_PP	Programming Enable Voltage	11.5	12.5	V
I_PP	Programming Enable Current		250	μA
t_DVXH	Data and Control Valid before XTAL1 High	67		ns
t_XLXH	XTAL1 Low to XTAL1 High	200		ns
t_XHXL	XTAL1 Pulse Width High	150		ns
t_XLDX	Data and Control Hold after XTAL1 Low	67		ns
t_XLWL	XTAL1 Low to WR Low	0		ns
t_XLPH	XTAL1 Low to PAGEL high	0		ns
t_PLXH	PAGEL low to XTAL1 high	150		ns
t_BVPH	BS1 Valid before PAGEL High	67		ns
t_PHPL	PAGEL Pulse Width High	150		ns
t_PLBX	BS1 Hold after PAGEL Low	67		ns
t_WLBX	BS2/1 Hold after WR Low	67		ns
t_PLWL	PAGEL Low to WR Low	67		ns
t_BVWL	BS1 Valid to WR Low	67		ns
t_WLWH	WR Pulse Width Low	150		ns
t_WLRL	WR Low to RDY/BSY Low	0	1	μs
t_WLRH	WR Low to RDY/BSY High⁽¹⁾	3.7	4.5	ms
t_{WLRH_CE}	WR Low to RDY/BSY High for Chip Erase⁽²⁾	7.5	9	ms
t_XLOL	XTAL1 Low to OE Low	0		ns
t_BVDV	BS1 Valid to DATA valid	0	250	ns
t_OLDV	OE Low to DATA Valid		250	ns
t_OHDZ	OE High to DATA Tri-stated		250	ns

Note:

t_WLRH is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write Lock Bits commands.
t_{WLRH_CE} is valid for the Chip Erase command.