11.1.7.7 Universal DDR Memory Controller (UDDRC) and DDR/LPDDR Physical Interface (DDR3PHY)
The UDDRC and DDR3PHY are compliant with the following JEDEC standards:
- DDR2-SDRAM: JESD79-2E with operating frequencies up to 533 MHz
- DDR3-SDRAM: JESD79-3C with operating frequencies up to 533 MHz
- DDR3L-SDRAM: JESD79-3-1A with operating frequencies up to 533 MHz
- LPDDR2-SDRAM: JESD209-2B with operating frequencies up to 533 MHz
- LPDDR3-SDRAM: JESD209-3B with operating frequencies up to 533 MHz
The physical interface (PCB layout) between the processor and its memory has a major impact on signal integrity. Microchip provides IBIS models of the SAMA7D6 device and strongly recommends to verify this processor-memory interface on a PCB simulation tool.