11.1.6.4.2 QSPI0 I/O Calibration
The device embeds a QSPI0 I/O calibration cell. The purpose of this block is to provide to octal/quad SPI I/Os an output impedance reference to limit the impact of process, voltage and temperature on the drivers output impedance. The impedance control is required at high frequency in order to improve signal quality.
The calibration cell provides an input pin QSPI0_CAL loaded with a 20 KΩ RZQ resistor for 1.8V memories and a 16.9 KΩ resistor for 3.3V memories. In the above figure, CZQ is not mounted.
According to the QSPI specification, the output impedance calibration is mandatory for QSPI Hyperflash mode (1.8V), whereas it is not for other modes (3.3V).
The following table provides the values to program in the QSPI_PCALCFG.CLKDIV field with respect to MCK5 clock frequency.
| CLKDIV | Divider | MCK5 (MHz) |
|---|---|---|
| 0 | 2 | 25 |
| 1 | 4 | 50 |
| 2 | 6 | 75 |
| 3 | 8 | 100 |
| 4 | 10 | 125 |
| 5 | 12 | 150 |
| 6 | 14 | 175 |
| 7 | 16 | 200 |