3.3.5.15 Changing Clock Frequencies

The process of changing clock frequencies using UDDRC_REGS_FREQ1 timing registers is as follows:

1. Program UDDRC_REGS_FREQ1 timing register-set with the timing settings required for the alternative clock frequency.
2. Write 0 to PCTRL_n.port_en. This blocks AXI port(s) from taking any transaction (blocks traffic on AXI ports).
3. Poll PSTAT.rd_port_busy_n=0 and PSTAT.wr_port_busy_n=0. Wait until all AXI ports are idle (the UDDRC controller has to be idle).
4. Poll DBGCAM.dbg_wr_q_empty and DBGCAM.dbg_rd_q_empty to ensure that write and read data buffers are empty.
5. Set DFILPCFG0.dfi_lp_en_sr = 0, if DFILPCFG0.dfi_lp_en_sr = 1, and wait until DFISTAT.dfi_lp_ack = 0.
6. Wait until STAT.operating_mode[1:0]!=11 indicating that the UDDRC is not in Self-Refresh mode.
7. Assert PWRCTL.selfref_sw for the UDDRC to enter Self-Refresh mode.
8. Wait until STAT.operating_mode[1:0]==11 indicating that the UDDRC is in Self-Refresh mode. Ensure transition to self-refresh was due to software by checking that STAT.selfref_-type[1:0]=2’b10.
9. Set DFIMISC.dfi_init_complete_en to 0. It ensures that the UDDRC initialization state machine is not reset if the PHY needs to perform some initialization after the frequency change.
10. Change the clock frequency to the UDDRC ensuring there are no glitches.
11. Toggle RFSHCTL3.refresh_update_level to allow the new refresh-related register values to propagate to the refresh logic.
12. Update the PHY registers, then trigger the initialization in the PHY. Refer to the section “DDR/LPDDR Physical Interface (DDR3PHY)” for details about initialization.
13. Reset DFILPCFG0.dfi_lp_en_sr = 1 if DFILPCFG0.dfi_lp_en_sr has been set to 0 in step 10.
14. Request the UDDRC to exit self-refresh by de-asserting PWRCTL.selfref_sw. Wait until STAT.operating_mode[1:0]!=11 indicating that the UDDRC is no longer in Self-Refresh mode.
15. If necessary due to timing values changing due to frequency change, perform MRS/MRW commands through the Mode Register Read/Write signals (MRCTRL0.mr_*/MRCTRL1.mr_*) to update MR register settings of the DRAM.
16. Enable HIF commands by setting DBG1.dis_hif=0.
17. Reset DERATEEN.derate_enable = 1 if DERATEEN.derate_enable has been set to 0 in step 6.
18. Write 1 to PCTRL_n.port_en. AXI port(s) are no longer blocked from taking transactions (Re-enable traffic on AXI ports).