3.3.5.7 Burst Mode Operation

An abnormal read or write transaction on the host interface contains enough data for one DDR BL8 transaction in Full Bus Width mode. The actual burst length used on the DFI interface is controlled by MSTR.burst_rdwr[3:0] and the data bus width (MSTR.data_bus_width). When the PI (PHY interface block before DFI) splits read/write commands, it sends them back-to-back (or as close as is allowed by the protocol). This means that no other reads/writes/activates/precharges can be sent to that bank, and no refreshes can be sent to that rank, between these commands. However, it is possible for a refresh to be sent to another rank at this time.