Single Data Rate (SDR) Transfers
In SDR mode, a single bit is sent on each I3CC_SCL clock. All data is transmitted in byte format, with no limit on the number of bytes transferred per data transfer. After the I3CC sends the address and R/W bit, or the I3CC transmits a byte of data to the target. The target must respond with the acknowledge signal (ACK). When a target does not respond with an ACK pulse, the I3CC aborts the transfer by issuing a STOP condition. The target must leave the I3CC_SDA line high so that the I3CC can abort the transfer.
The single data rate transfers are initiated by the application through the command as explained in Command and Response Structure.
Based on the command initiated by the application and device address pointed to by the DEV_INDEX field of the command, or in case of no DAT or DCT configuration on the DYNAMIC_ADDRESS field present on the queued command, the I3CC initiates the transfers on the bus.
The following table illustrates the decoded transfer type based on Transfer command and DAT or I2CNI3C command field in case of no DAT or DCT configuration.
| Transfer Command (Command Port) | DEVICE Field in DAT Structure | Decoded Transfer Type | |||
|---|---|---|---|---|---|
| CP | CMD[14] | Speed Mode | RnW | ||
| 0 | NA | 0 to 4 | 0 | 0 | I3C Private Write Transfer |
| 0 | NA | 0 to 4 | 1 | 0 | I3C Private Read Transfer |
| 1 | 0 | 0 | 0 | 0 | I3C Broadcast CCC Write Transfer |
| 1 | 1 | 0 | 0 | 0 | I3C Directed CCC Write Transfer |
| 1 | 1 | 0 | 1 | 0 | I3C Directed CCC Read Transfer |
| 0 | x | 0 to 2 | 0 | 1 | I2C Private Write Transfer |
| 0 | x | 0 to 2 | 1 | 1 | I2C Private Read Transfer |
| Others | Illegal Combination | ||||