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2 CPU and Interconnect
2.9 Boot Strategies
2.9.1 Standard Boot Strategy
2.9.1.7 Boot Configuration Packet
2.9.1.7.4 Configuring an SD Card/e.MMC Boot

Introduction
Reference Document
1 Overview
2 CPU and Interconnect
- 2.1 Event System
- 2.2 System Interconnect and Security (SIS)
- 2.3 Cortex-A7 Processor (Arm)
- 2.4 External Interrupt Controller (EIC)
- 2.5 Debug and Test
- 2.6 NIC-400 Global Programmer’s View (NICGPV)
- 2.7 Bus Matrix (MATRIX)
- 2.8 DMA Controller (XDMAC)
- 2.9 Boot Strategies
  - 2.9.1 Standard Boot Strategy
    - 2.9.1.1 Description
    - 2.9.1.2 ROM Code Flow Diagram
    - 2.9.1.3 Chip Setup
    - 2.9.1.4 NVM Boot Sequence
    - 2.9.1.5 Valid Code Detection
    - 2.9.1.6 Boot Configuration
    - 2.9.1.7 Boot Configuration Packet
      - 2.9.1.7.1 Monitor Disable Word
        Monitor Disable Word
      - 2.9.1.7.2 ROM Code Console Pins Muxing Word
        ROM Code Console Pins Muxing Word
      - 2.9.1.7.3 Device Specific Data Copy Disable Word
        Device Specific Data Copy Disable Word
      - 2.9.1.7.4 Configuring an SD Card/e.MMC Boot
        2.9.1.7.4.1 SD Card/e.MMC Memory Boot Configuration (First Word)
        SD Card/e.MMC Memory Boot Configuration (First Word)
        2.9.1.7.4.2 SD Card/e.MMC Memory Boot Configuration (Second Word)
        SD Card/e.MMC Memory Boot Configuration (Second Word)
        2.9.1.7.4.3 SD Card/e.MMC Memory Boot Configuration (Third Word)
        SD Card/e.MMC Memory Boot Configuration (Third Word)
        2.9.1.7.4.4 SD Card/e.MMC Memory Boot Configuration (Fourth Word)
        SD Card/e.MMC Memory Boot Configuration (Fourth Word)
      - 2.9.1.7.5 Configuring a QSPI Boot
      - 2.9.1.7.6 Configuring a NAND Flash Memory Boot
      - 2.9.1.7.7 Configuring an SPI Memory Boot
    - 2.9.1.8 Bootstrap Version Packet
    - 2.9.1.9 Detailed Memory Boot Procedures
    - 2.9.1.10 SAM-BA Monitor
  - 2.9.2 Secure Boot Strategy
  - 2.9.3 Bootstrap Image Format
  - 2.9.4 Booting with OTP Emulation Mode
  - 2.9.5 Software Considerations
  - 2.9.6 Hardware Considerations
3 Memories
4 System Controller
5 Analog Subsystem
6 Image Subsystem
7 Audio Subsystem
8 Security and Cryptography Subsystem
9 Connectivity Subsystem
10 USB Subsystem
11 Electrical and Mechanical Characteristics
12 Glossary
13 Revision History
Microchip Information