1.12 Peripheral Identifiers

Table 1-4. Peripheral Identifiers
Instance ID	Instance Name	Security ⁽³⁾	TZ Security Management	GIC SPI Interrupt	Clock Domain	PMC Clock Control	Generic Clock (GCLK)	Instance Description
0	DWDT	AS	–	SW	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Dual Watchdog Timer, Secure World
1	DWDT	NS	–	NSW	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Dual Watchdog Timer, Non–secure World
2	DWDT	AS	–	NSW_ALARM	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Dual Watchdog Timer, Non–secure World Alarm
3	SCKC	AS	–	–	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Slow Clock Controller
4	SHDWC	AS	–	X	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Shutdown Controller
5	RSTC	AS	–	X	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Reset Controller
6	RTC	AS	–	X	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Real–Time Clock
7	RTT	AS	–	X	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Real–Time Timer
8	CHIPID	PS	TZPM	–	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Chip Identifier
9	PMC	AS	–	X	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Power Management Controller
10	PIOA	PS	PIOA	X	MCK0	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	For PIO 0 to 31
11	PIOB	PS	PIOB	X	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	For PIO 32 to 63
12	PIOC	PS	PIOC	X	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	For PIO 64 to 95
13	PIOD	PS	PIOD	X	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	For PIO 96 to 127
14	PIOE	PS	PIOE	X	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	For PIO 128 to 141
15	PUF	PS	TZPM	X	MCK0	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	PUFSRAM
16	SECUMOD	AS	–	X	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Security Module
17	SECURAM	AS	–	X	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Secret RAM
18	SFR	PS	TZPM	–	MCK7	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Special Function Register
19	SFRBU	AS	–	–	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Special Function Register in Backup zone
20	HSMC	PS	MATRIX + TZPM	X	MCK5	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Static Memory Controller – NAND Flash Controller
21	XDMAC0	PS	XDMAC0	X	MCK6	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	DMA 0, mem to periph, 32 channels
22	XDMAC1	PS	XDMAC1	X	MCK6	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	DMA 1, mem to periph, 32 channels
23	XDMAC2	PS	XDMAC2	X	MCK1⁽⁴⁾	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	DMA 2, mem to mem, 8 channels
24	ACC	PS	TZPM	X	MCK7	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Analog Comparator Controller
25	ADC	PS	TZPM	X	GCLK⁽¹⁾	–	100	–	–	–	–	X	X	–	–	–	X	X	X	X	Analog–to–Digital Converter
26	AES	PS	TZPM	X	MCK6	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Advanced Encryption Standard
27	TZAESBASC	AS	TZPM	–	MCK8	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	TrustZone Advanced Encryption Standard Bridge – Address Space Controlller
28	ARM	PS	MMU	–	GCLK	–	50	–	–	X	–	–	X	–	–	–	X	X	X	X	Cortex–A7 Core 0. Generic timer clock
29	ASRC	PS	TZPM	X	MCK9	X	200	–	–	–	–	–	X	–	–	–	X	X	X	X	Asynchronous Sample Rate Converter
30	CPKCC	PS	TZPM	X	MCK0	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Classic Public Key Cryptography Controller
31	DDR3PHY	PS	TZC + TZPM	–	MCK2	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	DDR/LPDDR Physical Interface
32	UDDRC	PS	TZC + TZPM	–	MCK2	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Universal DDR Memory Controller
33	EIC	PS	TZPM	–	MCK7	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	External Interrupt Controller
34	FLEXCOM0	PS	TZPM	X	MCK7	X	34	–	–	–	–	X	–	–	–	–	X	X	X	X	FLEXCOM0. Max Generic Clock Frequency = FPCLOCK/3
35	FLEXCOM1	PS	TZPM	X	MCK7	X	34	–	–	–	–	X	–	–	–	–	X	X	X	X	FLEXCOM1. Max Generic Clock Frequency = FPCLOCK/3
36	FLEXCOM2	PS	TZPM	X	MCK7	X	34	–	–	–	–	X	–	–	–	–	X	X	X	X	FLEXCOM2. Max Generic Clock Frequency = FPCLOCK/3
37	FLEXCOM3	PS	TZPM	X	MCK7	X	34	–	–	–	–	X	–	–	–	–	X	X	X	X	FLEXCOM3. Max Generic Clock Frequency = FPCLOCK/3
38	FLEXCOM4	PS	TZPM	X	MCK8	X	34	–	–	–	–	X	–	–	–	–	X	X	X	X	FLEXCOM4. Max Generic Clock Frequency = FPCLOCK/3
39	FLEXCOM5	PS	TZPM	X	MCK8	X	34	–	–	–	–	X	–	–	–	–	X	X	X	X	FLEXCOM5. Max Generic Clock Frequency = FPCLOCK/3
40	FLEXCOM6	PS	TZPM	X	MCK8	X	34	–	–	–	–	X	–	–	–	–	X	X	X	X	FLEXCOM6. Max Generic Clock Frequency = FPCLOCK/3
41	FLEXCOM7	PS	TZPM	X	MCK8	X	34	–	–	–	–	X	–	–	–	–	X	X	X	X	FLEXCOM7. Max Generic Clock Frequency = FPCLOCK/3
42	FLEXCOM8	PS	TZPM	X	MCK9	X	34	–	–	–	–	X	–	–	–	–	X	X	X	X	FLEXCOM8. Max Generic Clock Frequency = FPCLOCK/3
43	FLEXCOM9	PS	TZPM	X	MCK9	X	34	–	–	–	–	X	–	–	–	–	X	X	X	X	FLEXCOM9. Max Generic Clock Frequency = FPCLOCK/3
44	FLEXCOM10	PS	TZPM	X	MCK9	X	34	–	–	–	–	X	–	–	–	–	X	X	X	X	FLEXCOM10. Max Generic Clock Frequency = FPCLOCK/3
45	GPU2DC	PS	TZPM	X	MCK3	X	533	–	–	–	X	–	–	–	–	–	X	X	X	X	Graphic Processor Unit 2D Composer
46	GMAC0	PS	TZPM	X	MCK6/MCK1⁽²⁾	X	125	–	–	–	–	–	–	X	–	–	–	X	X	X	Gigabit Ethernet MAC + TSN support
47	GMAC1	PS	TZPM	X	MCK6/MCK1⁽²⁾	X	125	–	–	–	–	–	–	X	–	–	–	X	X	X	Gigabit Ethernet MAC + TSN support
48	RESERVED	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Reserved
49	GMAC0	PS	same as GMAC0	TSU	MCK1	–	400	–	X	–	–	–	X	X	–	–	X	X	X	X	Gigabit Ethernet MAC – Timestamp Unit Generic Clock
50	GMAC1	PS	same as GMAC1	TSU	MCK1	–	400	–	X	–	–	–	X	X	–	–	X	X	X	X	Gigabit Ethernet MAC – Timestamp Unit Generic Clock
51	NICGPV0	AS	–	–	MCK6	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	NIC400 Global Programmer's View instance 0
52	NICGPV1	AS	–	–	MCK3⁽⁴⁾	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	NIC400 Global Programmer's View instance 1
53	ICM	PS	TZPM	X	MCK5	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Integrity Check Monitor
54	I2SMCC0	PS	TZPM	X	MCK9	X	100	–	–	–	–	–	X	–	–	–	X	X	X	X	Inter–IC Sound Controller 0
55	I2SMCC1	PS	TZPM	X	MCK9	X	100	–	–	–	–	–	X	–	–	–	X	X	X	X	Inter–IC Sound Controller 1
56	LCDC	PS	TZPM	X	MCK3⁽⁴⁾	X	90	–	–	–	–	–	–	–	–	–	X	X	X	X	LCD controller
57	MATRIX	AS	–	X	MCK5/MCK5	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	AHB Matrix
58	MCAN0	PS	TZPM	INT0	MCK5	X	80	–	–	–	–	–	–	–	–	X	X	X	X	X	Host CAN 0
59	MCAN1	PS	TZPM	INT0	MCK5	X	80	–	–	–	–	–	–	–	–	X	X	X	X	X	Host CAN 1
60	MCAN2	PS	TZPM	INT0	MCK5	X	80	–	–	–	–	–	–	–	–	X	X	X	X	X	Host CAN 2
61	MCAN3	PS	TZPM	INT0	MCK5	X	80	–	–	–	–	–	–	–	–	X	X	X	X	X	Host CAN 3
62	MCAN4	PS	TZPM	INT0	MCK5	X	80	–	–	–	–	–	–	–	–	X	X	X	X	X	Host CAN 4
63	OTPC	PS	TZPM	X	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	One Time Programmable Memory Controller
64	PDMC0	PS	TZPM	X	MCK9	X	80	–	–	–	–	–	X	–	–	–	X	X	X	X	Pulse Density Modulation Interface Controller 0
65	PDMC1	PS	TZPM	X	MCK9	X	80	–	–	–	–	–	X	–	–	–	X	X	X	X	Pulse Density Modulation Interface Controller 1
66	PIT64B0	PS	TZPM	X	MCK7	X	34	–	–	–	–	X	X	X	–	–	X	X	X	X	64–bit Periodic Interval Timer 0
67	PIT64B1	PS	TZPM	X	MCK7	X	34	–	–	–	–	X	X	X	–	–	X	X	X	X	64–bit Periodic Interval Timer 1
68	PIT64B2	PS	TZPM	X	MCK7	X	34	–	–	–	–	X	X	X	–	–	X	X	X	X	64–bit Periodic Interval Timer 2
69	PIT64B3	PS	TZPM	X	MCK8	X	34	–	–	–	–	X	X	X	–	–	X	X	X	X	64–bit Periodic Interval Timer 3
70	PIT64B4	PS	TZPM	X	MCK8	X	34	–	–	–	–	X	X	X	–	–	X	X	X	X	64–bit Periodic Interval Timer 4
71	PIT64B5	PS	TZPM	X	MCK8	X	34	–	–	–	–	X	X	X	–	–	X	X	X	X	64–bit Periodic Interval Timer 5
72	PWM	PS	TZPM	X	MCK7	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Pulse Width Modulation
73	QSPI0	PS	MATRIX + TZPM	X	MCK5/MCK5	X	400	–	X	–	–	X	–	–	–	–	X	X	X	X	Quad IO Serial Peripheral Interface 0
74	QSPI1	PS	MATRIX + TZPM	X	MCK5/MCK5	X	266	–	X	–	–	X	–	–	–	–	X	X	X	X	Quad IO Serial Peripheral Interface 1
75	SDMMC0	PS	TZPM	X	MCK1⁽⁴⁾	X	208	–	–	–	–	X	–	X	–	–	X	X	X	X	Ultra High Speed SD Host Controller 0 (e.MMC 5.1)
76	SDMMC1	PS	TZPM	X	MCK1⁽⁴⁾	X	208	–	–	–	–	X	–	X	–	–	X	X	X	X	Ultra High Speed SD Host Controller 1 (e.MMC 4.51)
77	SDMMC2	PS	TZPM	X	MCK1⁽⁴⁾	X	208	–	–	–	–	X	–	X	–	–	X	X	X	X	Ultra High Speed SD Host Controller 2 (e.MMC 4.51)
78	SHA	PS	TZPM	X	MCK6	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Secure Hash Algorithm
79	SPDIFRX	PS	TZPM	X	MCK9	X	150	–	–	–	–	–	X	–	–	–	X	X	X	X	Sony/Philips Digital Interface RX
80	SPDIFTX	PS	TZPM	X	MCK9	X	25	–	–	–	–	–	X	–	–	–	X	X	X	X	Sony/Philips Digital Interface TX
81	SSC0	PS	TZPM	X	MCK7	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Synchronous Serial Interface 0
82	SSC1	PS	TZPM	X	MCK8	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Synchronous Serial Interface 1
83	TC0	PS	TZPM	CHANNEL0	MCK8	X	34	–	–	–	–	X	X	X	–	–	X	X	X	X	32–bit Timer Counter 0 Channel 0. Max Generic Clock Frequency = FPCLOCK/3
84	TC0	PS	same as channel0	CHANNEL1	MCK8	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	32–bit Timer Counter 0 Channel 1
85	TC0	PS	same as channel0	CHANNEL2	MCK8	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	32–bit Timer Counter 0 Channel 2
86	TC1	PS	TZPM	CHANNEL0	MCK5	X	67	–	–	–	–	X	X	X	–	–	X	X	X	X	32–bit Timer Counter 1 Channel 1. Max Generic Clock Frequency = FPCLOCK/3
87	TC1	PS	same as channel0	CHANNEL1	MCK5	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	32–bit Timer Counter 1 Channel 1
88	TC1	PS	same as channel0	CHANNEL2	MCK5	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	32–bit Timer Counter 1 Channel 2
89	TCPCA	PS	TZPM	X	MCK5	X	0.033	–	–	–	–	–	–	–	–	–	–	X	X	X	USB Type–C Port Controller A
90	TCPCB	PS	TZPM	X	MCK5	X	0.033	–	–	–	–	–	–	–	–	–	–	X	X	X	USB Type–C Port Controller B
91	TDES	PS	TZPM	X	MCK6	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Triple Data Encryption Standard
92	TRNG	PS	TZPM	X	MCK6	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	True Random Number Generator
93	TZAESB	PS	TZPM	NS	MCK5	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	TrustZone Advanced Encryption Standard Bridge Non–Secure (Clocks and Interrupt)
94	TZAESB	AS	–	NS_SINT	MCK5	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	TrustZone Advanced Encryption Standard Bridge Non–Secure (Interrupt only)
95	TZAESB	PS	TZPM	S	MCK5	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	TrustZone Advanced Encryption Standard Bridge Secure (Interrupt only)
96	TZAESB	AS	–	S_SINT	MCK5	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	TrustZone Advanced Encryption Standard Bridge Secure (Interrupt only)
97	TZC	AS	AS	X	MCK6	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	TrustZone Address Space Controller (TZC400)
98	TZPM	AS	AS	–	MCK0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	TrustZone Peripheral Manager
99	UDPHSA	PS	MATRIX + TZPM	X	MCK5	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	USB Device High Speed A
100	UDPHSB	PS	MATRIX + TZPM	X	MCK5	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	USB Device High Speed B
101	UHPHS	PS	MATRIX + TZPM	X	MCK5	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	USB Host Controller High Speed
102	RESERVED	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Reserved
103	DSI	PS	TZPM	X	MCK3⁽⁴⁾	X	27	–	X	–	–	–	–	–	–	–	X	X	X	X	Display Serial Interface Host interrupt and MIPI D-PHY clock
104	LVDSC	PS	TZPM	–	MCK3⁽⁴⁾	X	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Display Serial Interface between LCDC and LVDS interface. Instance includes LVDSC and LVDSPHY
105	I3CC	PS	TZPM	X	MCK8	X	125	–	–	–	–	X	X	X	–	–	X	X	X	X	I3C Controller
106	RESERVED	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Reserved
107	ARM	PS	MMU	nPMUIRQ	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Performance Monitoring Unit
108	ARM	PS	MMU	nAXIERRIRQ	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	AXI Transaction Error
109	XDMAC0	PS	XDMAC0	SINT	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	DMA0, mem to periph, 32 channels, Secure Interrupt
110	XDMAC1	PS	XDMAC1	SINT	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	DMA1, mem to periph, 32 channels, Secure Interrupt
111	XDMAC2	PS	XDMAC2	SINT	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	DMA2, mem to mem, 8 channels, Secure Interrupt
112	AES	PS	same as AES	SINT	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Advanced Encryption Standard, Secure Interrupt
113	ICM	PS	same as ICM	SINT	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Integrity Check Monitor, Secure Interrupt
114	MCAN0	PS	same as MCAN0	INT1	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	MCAN0 Interrupt1
115	MCAN1	PS	same as MCAN1	INT1	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	MCAN1 Interrupt1
116	MCAN2	PS	same as MCAN2	INT1	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	MCAN2 Interrupt1
117	MCAN3	PS	same as MCAN3	INT1	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	MCAN3 Interrupt1
118	MCAN4	PS	same as MCAN4	INT1	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	MCAN4 Interrupt1
119	PIOA	PS	same as PIOA	SINT	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	For PIO 0 to 31, Secure Interrupt
120	PIOB	PS	same as PIOB	SINT	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	For PIO 32 to 63, Secure Interrupt
121	PIOC	PS	same as PIOC	SINT	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	For PIO 64 to 95, Secure Interrupt
122	PIOD	PS	same as PIOD	SINT	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	For PIO 96 to 127, Secure Interrupt
123	PIOE	PS	same as PIOE	SINT	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	For PIO 128 to 141, Secure Interrupt
124	RESERVED	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Reserved
125	RESERVED	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Reserved
126	RESERVED	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Reserved
127	RESERVED	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Reserved
128	RESERVED	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Reserved
129	RESERVED	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Reserved
130	SDMMC0	PS	same as SDMMC0	TIMER	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Ultra High Speed SD Host Controller 0 (e.MMC 5.1) Timer interrupt
131	SDMMC1	PS	same as SDMMC1	TIMER	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Ultra High Speed SD Host Controller 1 (e.MMC 4.51) Timer interrupt
132	SDMMC2	PS	same as SDMMC2	TIMER	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Ultra High Speed SD Host controller 2 (e.MMC 4.51) Timer interrupt
133	SHA	PS	same as SHA	SINT	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Secure Hash Algorithm, Secure Interrupt
134	RESERVED	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Reserved
135	RESERVED	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Reserved
136	RESERVED	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Reserved
137	RESERVED	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Reserved
138	RESERVED	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Reserved
139	RESERVED	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Reserved
140	TDES	PS	same as TDES	SINT	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	Triple Data Encryption Standard, Secure Interrupt
141	TRNG	PS	same as TRNG	SINT	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	True Random Number Generator, Secure Interrupt
142	EIC	PS	same as EIC	EXT_IRQ0	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	External Interrupt ID0
143	EIC	PS	same as EIC	EXT_IRQ1	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	External Interrupt ID1
144	GMAC0	PS	same as GMAC0	Q1	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	GMAC0 Queue 1 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 1
145	GMAC0	PS	same as GMAC0	Q2	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	GMAC0 Queue 2 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 2
146	GMAC0	PS	same as GMAC0	Q3	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	GMAC0 Queue 3 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 3
147	GMAC0	PS	same as GMAC0	Q4	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	GMAC0 Queue 4 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 4
148	GMAC0	PS	same as GMAC0	Q5	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	GMAC0 Queue 5 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 5
149	GMAC0	PS	same as GMAC0	EMAC	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	GMAC0: Express MAC
150	GMAC0	PS	same as GMAC0	MMSL	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	GMAC0: MAC Merge Sublayer
151	GMAC1	PS	same as GMAC1	Q1	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	GMAC1 Queue 1 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 1
152	GMAC1	PS	same as GMAC1	Q2	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	GMAC1 Queue 2 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 2
153	GMAC1	PS	same as GMAC1	Q3	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	GMAC1 Queue 3 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 3
154	GMAC1	PS	same as GMAC1	Q4	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	GMAC1 Queue 4 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 4
155	GMAC1	PS	same as GMAC1	Q5	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	GMAC1 Queue 5 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 5
156	GMAC1	PS	same as GMAC1	EMAC	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	GMAC1: Express MAC
157	GMAC1	PS	same as GMAC1	MMSL	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	–	GMAC1: MAC Merge Sublayer
Warning: GCLK must be started before accessing registers. Note: Select GCLK input as MD_SLCK or TD_SLCK. Both domain clocks must be enabled for the peripheral to work properly. AS: Always Secure, PS: Programmable Secure, NS: Never Secure. For proper operation, enable the MCK6 domain clock in addition to the peripheral domain clock.

0

DWDT

AS

–

SW

MCK0

–

Dual Watchdog Timer, Secure World

1

DWDT

NS

–

NSW

MCK0

–

Dual Watchdog Timer, Non–secure World

2

DWDT

AS

–

NSW_ALARM

MCK0

–

Dual Watchdog Timer, Non–secure World Alarm

3

SCKC

AS

–

MCK0

–

Slow Clock Controller

4

SHDWC

AS

–

X

MCK0

–

Shutdown Controller

5

RSTC

AS

–

X

MCK0

–

Reset Controller

6

RTC

AS

–

X

MCK0

–

Real–Time Clock

7

RTT

AS

–

X

MCK0

–

Real–Time Timer

8

CHIPID

PS

TZPM

–

MCK0

–

Chip Identifier

9

PMC

AS

–

X

MCK0

–

Power Management Controller

10

PIOA

PS

PIOA

X

MCK0

X

–

For PIO 0 to 31

11

PIOB

PS

PIOB

X

MCK0

–

For PIO 32 to 63

12

PIOC

PS

PIOC

X

MCK0

–

For PIO 64 to 95

13

PIOD

PS

PIOD

X

MCK0

–

For PIO 96 to 127

14

PIOE

PS

PIOE

X

MCK0

–

For PIO 128 to 141

15

PUF

PS

TZPM

X

MCK0

X

–

PUFSRAM

16

SECUMOD

AS

–

X

MCK0

–

Security Module

17

SECURAM

AS

–

X

MCK0

–

Secret RAM

18

SFR

PS

TZPM

–

MCK7

X

–

Special Function Register

19

SFRBU

AS

–

MCK0

–

Special Function Register in Backup zone

20

HSMC

PS

MATRIX + TZPM

X

MCK5

X

–

Static Memory Controller – NAND Flash Controller

21

XDMAC0

PS

XDMAC0

X

MCK6

X

–

DMA 0, mem to periph, 32 channels

22

XDMAC1

PS

XDMAC1

X

MCK6

X

–

DMA 1, mem to periph, 32 channels

23

XDMAC2

PS

XDMAC2

X

MCK1⁽⁴⁾

X

–

DMA 2, mem to mem, 8 channels

24

ACC

PS

TZPM

X

MCK7

X

–

Analog Comparator Controller

25

ADC

PS

TZPM

X

GCLK⁽¹⁾

–

100

–

X

–

X

Analog–to–Digital Converter

26

AES

PS

TZPM

X

MCK6

X

–

Advanced Encryption Standard

27

TZAESBASC

AS

TZPM

–

MCK8

X

–

TrustZone Advanced Encryption Standard Bridge – Address Space Controlller

28

ARM

PS

MMU

–

GCLK

–

50

–

X

–

X

–

X

Cortex–A7 Core 0. Generic timer clock

29

ASRC

PS

TZPM

X

MCK9

X

200

–

X

–

X

Asynchronous Sample Rate Converter

30

CPKCC

PS

TZPM

X

MCK0

X

–

Classic Public Key Cryptography Controller

31

DDR3PHY

PS

TZC + TZPM

–

MCK2

–

DDR/LPDDR Physical Interface

32

UDDRC

PS

TZC + TZPM

–

MCK2

X

–

Universal DDR Memory Controller

33

EIC

PS

TZPM

–

MCK7

X

–

External Interrupt Controller

34

FLEXCOM0

PS

TZPM

X

MCK7

X

34

–

X

–

X

FLEXCOM0. Max Generic Clock Frequency = FPCLOCK/3

35

FLEXCOM1

PS

TZPM

X

MCK7

X

34

–

X

–

X

FLEXCOM1. Max Generic Clock Frequency = FPCLOCK/3

36

FLEXCOM2

PS

TZPM

X

MCK7

X

34

–

X

–

X

FLEXCOM2. Max Generic Clock Frequency = FPCLOCK/3

37

FLEXCOM3

PS

TZPM

X

MCK7

X

34

–

X

–

X

FLEXCOM3. Max Generic Clock Frequency = FPCLOCK/3

38

FLEXCOM4

PS

TZPM

X

MCK8

X

34

–

X

–

X

FLEXCOM4. Max Generic Clock Frequency = FPCLOCK/3

39

FLEXCOM5

PS

TZPM

X

MCK8

X

34

–

X

–

X

FLEXCOM5. Max Generic Clock Frequency = FPCLOCK/3

40

FLEXCOM6

PS

TZPM

X

MCK8

X

34

–

X

–

X

FLEXCOM6. Max Generic Clock Frequency = FPCLOCK/3

41

FLEXCOM7

PS

TZPM

X

MCK8

X

34

–

X

–

X

FLEXCOM7. Max Generic Clock Frequency = FPCLOCK/3

42

FLEXCOM8

PS

TZPM

X

MCK9

X

34

–

X

–

X

FLEXCOM8. Max Generic Clock Frequency = FPCLOCK/3

43

FLEXCOM9

PS

TZPM

X

MCK9

X

34

–

X

–

X

FLEXCOM9. Max Generic Clock Frequency = FPCLOCK/3

44

FLEXCOM10

PS

TZPM

X

MCK9

X

34

–

X

–

X

FLEXCOM10. Max Generic Clock Frequency = FPCLOCK/3

45

GPU2DC

PS

TZPM

X

MCK3

X

533

–

X

–

X

Graphic Processor Unit 2D Composer

46

GMAC0

PS

TZPM

X

MCK6/MCK1⁽²⁾

X

125

–

X

–

X

Gigabit Ethernet MAC + TSN support

47

GMAC1

PS

TZPM

X

MCK6/MCK1⁽²⁾

X

125

–

X

–

X

Gigabit Ethernet MAC + TSN support

48

RESERVED

–

Reserved

49

GMAC0

PS

same as GMAC0

TSU

MCK1

–

400

–

X

–

X

–

X

Gigabit Ethernet MAC – Timestamp Unit Generic Clock

50

GMAC1

PS

same as GMAC1

TSU

MCK1

–

400

–

X

–

X

–

X

Gigabit Ethernet MAC – Timestamp Unit Generic Clock

51

NICGPV0

AS

–

MCK6

X

–

NIC400 Global Programmer's View instance 0

52

NICGPV1

AS

–

MCK3⁽⁴⁾

X

–

NIC400 Global Programmer's View instance 1

53

ICM

PS

TZPM

X

MCK5

X

–

Integrity Check Monitor

54

I2SMCC0

PS

TZPM

X

MCK9

X

100

–

X

–

X

Inter–IC Sound Controller 0

55

I2SMCC1

PS

TZPM

X

MCK9

X

100

–

X

–

X

Inter–IC Sound Controller 1

56

LCDC

PS

TZPM

X

MCK3⁽⁴⁾

X

90

–

X

LCD controller

57

MATRIX

AS

–

X

MCK5/MCK5

X

–

AHB Matrix

58

MCAN0

PS

TZPM

INT0

MCK5

X

80

–

X

Host CAN 0

59

MCAN1

PS

TZPM

INT0

MCK5

X

80

–

X

Host CAN 1

60

MCAN2

PS

TZPM

INT0

MCK5

X

80

–

X

Host CAN 2

61

MCAN3

PS

TZPM

INT0

MCK5

X

80

–

X

Host CAN 3

62

MCAN4

PS

TZPM

INT0

MCK5

X

80

–

X

Host CAN 4

63

OTPC

PS

TZPM

X

MCK0

–

One Time Programmable Memory Controller

64

PDMC0

PS

TZPM

X

MCK9

X

80

–

X

–

X

Pulse Density Modulation Interface Controller 0

65

PDMC1

PS

TZPM

X

MCK9

X

80

–

X

–

X

Pulse Density Modulation Interface Controller 1

66

PIT64B0

PS

TZPM

X

MCK7

X

34

–

X

–

X

64–bit Periodic Interval Timer 0

67

PIT64B1

PS

TZPM

X

MCK7

X

34

–

X

–

X

64–bit Periodic Interval Timer 1

68

PIT64B2

PS

TZPM

X

MCK7

X

34

–

X

–

X

64–bit Periodic Interval Timer 2

69

PIT64B3

PS

TZPM

X

MCK8

X

34

–

X

–

X

64–bit Periodic Interval Timer 3

70

PIT64B4

PS

TZPM

X

MCK8

X

34

–

X

–

X

64–bit Periodic Interval Timer 4

71

PIT64B5

PS

TZPM

X

MCK8

X

34

–

X

–

X

64–bit Periodic Interval Timer 5

72

PWM

PS

TZPM

X

MCK7

X

–

Pulse Width Modulation

73

QSPI0

PS

MATRIX + TZPM

X

MCK5/MCK5

X

400

–

X

–

X

–

X

Quad IO Serial Peripheral Interface 0

74

QSPI1

PS

MATRIX + TZPM

X

MCK5/MCK5

X

266

–

X

–

X

–

X

Quad IO Serial Peripheral Interface 1

75

SDMMC0

PS

TZPM

X

MCK1⁽⁴⁾

X

208

–

X

–

X

–

X

Ultra High Speed SD Host Controller 0 (e.MMC 5.1)

76

SDMMC1

PS

TZPM

X

MCK1⁽⁴⁾

X

208

–

X

–

X

–

X

Ultra High Speed SD Host Controller 1 (e.MMC 4.51)

77

SDMMC2

PS

TZPM

X

MCK1⁽⁴⁾

X

208

–

X

–

X

–

X

Ultra High Speed SD Host Controller 2 (e.MMC 4.51)

78

SHA

PS

TZPM

X

MCK6

X

–

Secure Hash Algorithm

79

SPDIFRX

PS

TZPM

X

MCK9

X

150

–

X

–

X

Sony/Philips Digital Interface RX

80

SPDIFTX

PS

TZPM

X

MCK9

X

25

–

X

–

X

Sony/Philips Digital Interface TX

81

SSC0

PS

TZPM

X

MCK7

X

–

Synchronous Serial Interface 0

82

SSC1

PS

TZPM

X

MCK8

X

–

Synchronous Serial Interface 1

83

TC0

PS

TZPM

CHANNEL0

MCK8

X

34

–

X

–

X

32–bit Timer Counter 0 Channel 0. Max Generic Clock Frequency = FPCLOCK/3

84

TC0

PS

same as channel0

CHANNEL1

MCK8

X

–

32–bit Timer Counter 0 Channel 1

85

TC0

PS

same as channel0

CHANNEL2

MCK8

X

–

32–bit Timer Counter 0 Channel 2

86

TC1

PS

TZPM

CHANNEL0

MCK5

X

67

–

X

–

X

32–bit Timer Counter 1 Channel 1. Max Generic Clock Frequency = FPCLOCK/3

87

TC1

PS

same as channel0

CHANNEL1

MCK5

X

–

32–bit Timer Counter 1 Channel 1

88

TC1

PS

same as channel0

CHANNEL2

MCK5

X

–

32–bit Timer Counter 1 Channel 2

89

TCPCA

PS

TZPM

X

MCK5

X

0.033

–

X

USB Type–C Port Controller A

90

TCPCB

PS

TZPM

X

MCK5

X

0.033

–

X

USB Type–C Port Controller B

91

TDES

PS

TZPM

X

MCK6

X

–

Triple Data Encryption Standard

92

TRNG

PS

TZPM

X

MCK6

X

–

True Random Number Generator

93

TZAESB

PS

TZPM

NS

MCK5

X

–

TrustZone Advanced Encryption Standard Bridge Non–Secure (Clocks and Interrupt)

94

TZAESB

AS

–

NS_SINT

MCK5

–

TrustZone Advanced Encryption Standard Bridge Non–Secure (Interrupt only)

95

TZAESB

PS

TZPM

S

MCK5

–

TrustZone Advanced Encryption Standard Bridge Secure (Interrupt only)

96

TZAESB

AS

–

S_SINT

MCK5

–

TrustZone Advanced Encryption Standard Bridge Secure (Interrupt only)

97

TZC

AS

X

MCK6

–

TrustZone Address Space Controller (TZC400)

98

TZPM

AS

–

MCK0

–

TrustZone Peripheral Manager

99

UDPHSA

PS

MATRIX + TZPM

X

MCK5

X

–

USB Device High Speed A

100

UDPHSB

PS

MATRIX + TZPM

X

MCK5

X

–

USB Device High Speed B

101

UHPHS

PS

MATRIX + TZPM

X

MCK5

X

–

USB Host Controller High Speed

102

RESERVED

–

Reserved

103

DSI

PS

TZPM

X

MCK3⁽⁴⁾

X

27

–

X

–

X

Display Serial Interface Host interrupt and MIPI D-PHY clock

104

LVDSC

PS

TZPM

–

MCK3⁽⁴⁾

X

–

Display Serial Interface between LCDC and LVDS interface. Instance includes LVDSC and LVDSPHY

105

I3CC

PS

TZPM

X

MCK8

X

125

–

X

–

X

I3C Controller

106

RESERVED

–

Reserved

107

ARM

PS

MMU

nPMUIRQ

–

Performance Monitoring Unit

108

ARM

PS

MMU

nAXIERRIRQ

–

AXI Transaction Error

109

XDMAC0

PS

XDMAC0

SINT

–

DMA0, mem to periph, 32 channels, Secure Interrupt

110

XDMAC1

PS

XDMAC1

SINT

–

DMA1, mem to periph, 32 channels, Secure Interrupt

111

XDMAC2

PS

XDMAC2

SINT

–

DMA2, mem to mem, 8 channels, Secure Interrupt

112

AES

PS

same as AES

SINT

–

Advanced Encryption Standard, Secure Interrupt

113

ICM

PS

same as ICM

SINT

–

Integrity Check Monitor, Secure Interrupt

114

MCAN0

PS

same as MCAN0

INT1

–

MCAN0 Interrupt1

115

MCAN1

PS

same as MCAN1

INT1

–

MCAN1 Interrupt1

116

MCAN2

PS

same as MCAN2

INT1

–

MCAN2 Interrupt1

117

MCAN3

PS

same as MCAN3

INT1

–

MCAN3 Interrupt1

118

MCAN4

PS

same as MCAN4

INT1

–

MCAN4 Interrupt1

119

PIOA

PS

same as PIOA

SINT

–

For PIO 0 to 31, Secure Interrupt

120

PIOB

PS

same as PIOB

SINT

–

For PIO 32 to 63, Secure Interrupt

121

PIOC

PS

same as PIOC

SINT

–

For PIO 64 to 95, Secure Interrupt

122

PIOD

PS

same as PIOD

SINT

–

For PIO 96 to 127, Secure Interrupt

123

PIOE

PS

same as PIOE

SINT

–

For PIO 128 to 141, Secure Interrupt

124

RESERVED

–

Reserved

125

RESERVED

–

Reserved

126

RESERVED

–

Reserved

127

RESERVED

–

Reserved

128

RESERVED

–

Reserved

129

RESERVED

–

Reserved

130

SDMMC0

PS

same as SDMMC0

TIMER

–

Ultra High Speed SD Host Controller 0 (e.MMC 5.1) Timer interrupt

131

SDMMC1

PS

same as SDMMC1

TIMER

–

Ultra High Speed SD Host Controller 1 (e.MMC 4.51) Timer interrupt

132

SDMMC2

PS

same as SDMMC2

TIMER

–

Ultra High Speed SD Host controller 2 (e.MMC 4.51) Timer interrupt

133

SHA

PS

same as SHA

SINT

–

Secure Hash Algorithm, Secure Interrupt

134

RESERVED

–

Reserved

135

RESERVED

–

Reserved

136

RESERVED

–

Reserved

137

RESERVED

–

Reserved

138

RESERVED

–

Reserved

139

RESERVED

–

Reserved

140

TDES

PS

same as TDES

SINT

–

Triple Data Encryption Standard, Secure Interrupt

141

TRNG

PS

same as TRNG

SINT

–

True Random Number Generator, Secure Interrupt

142

EIC

PS

same as EIC

EXT_IRQ0

–

External Interrupt ID0

143

EIC

PS

same as EIC

EXT_IRQ1

–

External Interrupt ID1

144

GMAC0

PS

same as GMAC0

Q1

–

GMAC0 Queue 1 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 1

145

GMAC0

PS

same as GMAC0

Q2

–

GMAC0 Queue 2 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 2

146

GMAC0

PS

same as GMAC0

Q3

–

GMAC0 Queue 3 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 3

147

GMAC0

PS

same as GMAC0

Q4

–

GMAC0 Queue 4 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 4

148

GMAC0

PS

same as GMAC0

Q5

–

GMAC0 Queue 5 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 5

149

GMAC0

PS

same as GMAC0

EMAC

–

GMAC0: Express MAC

150

GMAC0

PS

same as GMAC0

MMSL

–

GMAC0: MAC Merge Sublayer

151

GMAC1

PS

same as GMAC1

Q1

–

GMAC1 Queue 1 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 1

152

GMAC1

PS

same as GMAC1

Q2

–

GMAC1 Queue 2 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 2

153

GMAC1

PS

same as GMAC1

Q3

–

GMAC1 Queue 3 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 3

154

GMAC1

PS

same as GMAC1

Q4

–

GMAC1 Queue 4 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 4

155

GMAC1

PS

same as GMAC1

Q5

–

GMAC1 Queue 5 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 5

156

GMAC1

PS

same as GMAC1

EMAC

–

GMAC1: Express MAC

157

GMAC1

PS

same as GMAC1

MMSL

–

GMAC1: MAC Merge Sublayer

Warning: GCLK must be started before accessing registers.

Note:

Select GCLK input as MD_SLCK or TD_SLCK.
Both domain clocks must be enabled for the peripheral to work properly.
AS: Always Secure, PS: Programmable Secure, NS: Never Secure.
For proper operation, enable the MCK6 domain clock in addition to the peripheral domain clock.