43.3 Operation

A single clock running at the system bus frequency is used for all internal logic and both AHB interfaces.

The CTRLA.ENABLE and CTRLA.RUNSTDBY bits control operation of the clock. When CTRLA.ENABLE = 1 the clock is enabled in Active and Idle sleep modes. When CTRLA.ENABLE = 1 and CTRLA.RUNSTDBY = 1 the clock is also requested in standby sleep mode.

HSM-Lite has three interrupt requests. Interrupt processing functions are included in the Microchip Harmony Libraries.

The CTRLA.PRIV bit controls access to the HSM-Lite registers. When CTRLA.PRIV = 1, only privileged accesses are permitted to the HSM-Lite registers, unprivileged accesses generate a bus error. When CTRLA.PRIV = 0 both privileged and unprivileged accesses are permitted.

The CTRLA and WPCTRL registers can be write locked. This is controlled through the WPCTRL.WPEN and WPCTRL.WPLCK bits.