43.4 Cryptographic Accelerators

The AES accelerator supports 128, 192 and 256 bit key sizes and the following modes of operation: ECB, CBC, OFB, CFB, CTR, GCM, CCM, XTS, OMAC1, and CMAC. Ciphertext and plaintext data are transferred through the AHB Host port.

The Hash accelerator supports the SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512 hashes. HMAC processing is supported for all hashes. Message data is read through the AHB Host port.

The Public Key (PK) accelerator implements the following algorithms: RSA, DSA, DH, ECDH, ECDSA, EdDSA, J-PAKE and SRP. RSA, DSA and DH algorithms support up to 4096 bit key sizes. Standard ECC curves include: P-256, P-384 and 25519. Other ECC curves are supported through custom parameters including Brainpool, Koblitz, Montgomery, and Edwards.

Up to 16 Kb of system RAM is used for PK inputs, outputs, and scratch pad RAM. The location and size of the PK RAM area is programmable. Likewise 8 Kb of Boot ROM is used for PK microcode. The AHB Host port is used for fetching.