43.8 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	CTRLA	31:24
		23:16
		15:8
		7:0		RUNSTDBY				PRIV	ENABLE	SWRST
0x04 ... 0x37	Reserved
0x38	STATUSA	31:24
		23:16
		15:8
		7:0								OTPLOCK
0x3C ... 0x5B	Reserved
0x5C	SYNCBUSY	31:24
		23:16
		15:8
		7:0							ENABLE	SWRST
0x60 ... 0xDF	Reserved
0xE0	WPCTRL	31:24	WPKEY[23:16]
		23:16	WPKEY[15:8]
		15:8	WPKEY[7:0]
		7:0							WPLCK	WPEN
0xE4 ... 0xFFFF	Reserved
0x010000	CryptoMaster_DMA_Registers__FETCH_ADDR_LSB	31:24	FETCH_ADDR_LSB[31:24]
		23:16	FETCH_ADDR_LSB[23:16]
		15:8	FETCH_ADDR_LSB[15:8]
		7:0	FETCH_ADDR_LSB[7:0]
0x010004	CryptoMaster_DMA_Registers__FETCH_ADDR_MSB	31:24	FETCH_ADDR_MSB[31:24]
		23:16	FETCH_ADDR_MSB[23:16]
		15:8	FETCH_ADDR_MSB[15:8]
		7:0	FETCH_ADDR_MSB[7:0]
0x010008	CryptoMaster_DMA_Registers__FETCH_LEN	31:24		FETCH_ZPADDING	FETCH_REALIGN	FETCH_CSTADDR	FETCH_LEN[27:24]
		23:16	FETCH_LEN[23:16]
		15:8	FETCH_LEN[15:8]
		7:0	FETCH_LEN[7:0]
0x01000C	CryptoMaster_DMA_Registers__FETCH_TAG	31:24	FETCH_TAG[31:24]
		23:16	FETCH_TAG[23:16]
		15:8	FETCH_TAG[15:8]
		7:0	FETCH_TAG[7:0]
0x010010	CryptoMaster_DMA_Registers__PUSH_ADDR_LSB	31:24	PUSH_ADDR_LSB[31:24]
		23:16	PUSH_ADDR_LSB[23:16]
		15:8	PUSH_ADDR_LSB[15:8]
		7:0	PUSH_ADDR_LSB[7:0]
0x010014	CryptoMaster_DMA_Registers__PUSH_ADDR_MSB	31:24	PUSH_ADDR_MSB[31:24]
		23:16	PUSH_ADDR_MSB[23:16]
		15:8	PUSH_ADDR_MSB[15:8]
		7:0	PUSH_ADDR_MSB[7:0]
0x010018	CryptoMaster_DMA_Registers__PUSH_LEN	31:24		PUSH_DISCARD	PUSH_REALIGN	PUSH_CSTADDR	PUSH_LEN[27:24]
		23:16	PUSH_LEN[23:16]
		15:8	PUSH_LEN[15:8]
		7:0	PUSH_LEN[7:0]
0x01001C	CryptoMaster_DMA_Registers__INT_EN	31:24
		23:16
		15:8
		7:0			INT_EN[5:0]
0x010020	CryptoMaster_DMA_Registers__INT_ENSET	31:24
		23:16
		15:8
		7:0			INT_ENSET[5:0]
0x010024	CryptoMaster_DMA_Registers__INT_ENCLR	31:24
		23:16
		15:8
		7:0			INT_ENCLR[5:0]
0x010028	CryptoMaster_DMA_Registers__INT_STATRAW	31:24
		23:16
		15:8
		7:0			INT_STATRAW[5:0]
0x01002C	CryptoMaster_DMA_Registers__INT_STAT	31:24
		23:16
		15:8
		7:0			INT_STAT[5:0]
0x010030	CryptoMaster_DMA_Registers__INT_STATCLR	31:24
		23:16
		15:8
		7:0			INT_STATCLR[5:0]
0x010034	CryptoMaster_DMA_Registers__CONFIG	31:24
		23:16
		15:8
		7:0				SOFT_RST	PUSH_STOP	FETCH_STOP	PUSH_CTRL_INDIRECT	FETCH_CTRL_INDIRECT
0x010038	CryptoMaster_DMA_Registers__START	31:24
		23:16
		15:8
		7:0							START_PUSH	START_FETCH
0x01003C	CryptoMaster_DMA_Registers__STATUS	31:24	PUSH_NBDATA[15:8]
		23:16	PUSH_NBDATA[7:0]
		15:8
		7:0		SOFT_RST_BUSY	PUSH_WAITINGFIFO	FETCH_NOT_EMPTY			PUSH_BUSY	FETCH_BUSY
0x010040 ... 0x0103FF	Reserved
0x010400	CryptoMaster_HWConf_Registers__INCL_IPS_HW_CFG	31:24
		23:16
		15:8			BA422_KASUMI_INCLUDED	BA423_SNOW3G_INCLUDED	BA420_HP_CHACHAPOLY_INCLUDED	BA431_NDRNG_INCLUDED	BA414EP_PKE_INCLUDED	BA419_SM4_INCLUDED
		7:0	BA421_ZUC_INCLUDED	BA418_SHA3_INCLUDED	BA417_CHACHAPOLY_INCLUDED	BA413_HASH_INCLUDED	BA412_DES_INCLUDED	BA416_HP_AES_XTS_INCLUDED	BA415_HP_AES_GCM_INCLUDED	BA411_AES_INCLUDED
0x010404	CryptoMaster_HWConf_Registers__BA411E_AES_HW_CFG_1	31:24				BA411E_AES_HW_CFG_GLITCHPROTECTION	BA411E_AES_HW_CFG_CXSWITCH	BA411E_AES_HW_CFG_KEYSIZE[2:0]
		23:16							BA411E_AES_HW_CFG_MASKING	BA411E_AES_HW_CFG_CS
		15:8								BA411E_AES_HW_CFG_MODE[8]
		7:0	BA411E_AES_HW_CFG_MODE[7:0]
0x010408	CryptoMaster_HWConf_Registers__BA411E_AES_HW_CFG_2	31:24					BA411E_AES_HW_CFG_2_IKGKEYS[3:0]
		23:16	BA411E_AES_HW_CFG_2_EXTKEYS[3:0]
		15:8	BA411E_AES_HW_CFG_2_CTRSIZE[15:8]
		7:0	BA411E_AES_HW_CFG_2_CTRSIZE[7:0]
0x01040C	CryptoMaster_HWConf_Registers__BA413_HASH_HW_CFG	31:24					BA413_HASH_HW_CFG_IKGKEYS[3:0]
		23:16	BA413_HASH_HW_CFG_EXTKEYS[3:0]					BA413_HASH_HW_CFG_VERIFYDIGEST	BA413_HASH_HW_CFG_HMAC	BA413_HASH_HW_CFG_PADDING
		15:8
		7:0		BA413_HASH_HW_CFG_MASK[6:0]
0x010410	CryptoMaster_HWConf_Registers__BA418_SHA3_HW_CFG	31:24
		23:16
		15:8
		7:0								BA418_SHA3_HW_CFG
0x010414	CryptoMaster_HWConf_Registers__BA419_SM4_HW_CFG	31:24
		23:16
		15:8								BA419_SM4_HW_CFG[8]
		7:0	BA419_SM4_HW_CFG[7:0]
0x010418	CryptoMaster_HWConf_Registers__BA424_ARIA_HW_CFG	31:24
		23:16
		15:8								BA424_ARIA_HW_CFG[8]
		7:0	BA424_ARIA_HW_CFG[7:0]
0x01041C ... 0x010FFF	Reserved
0x011000	RNG_Control_Registers__Control	31:24
		23:16				FifoWriteStartUp	Nb128BitBlocks[3:0]
		15:8	AIS31TestSel	HealthTestSel	AIS31Bypass	HealthTestBypass	ForceActiveROs	IntEnAlm	IntEnPre	SoftRst
		7:0	IntEnFull		IntEnProp	IntEnRep	CondBypass	TestEn	LFSREn	Enable
0x011004	RNG_Control_Registers__FIFOLevel	31:24	FIFOLevel[31:24]
		23:16	FIFOLevel[23:16]
		15:8	FIFOLevel[15:8]
		7:0	FIFOLevel[7:0]
0x011008	RNG_Control_Registers__FIFOThreshold	31:24
		23:16
		15:8
		7:0							FIFOThreshold[1:0]
0x01100C	RNG_Control_Registers__FIFODepth	31:24	FIFODepth[31:24]
		23:16	FIFODepth[23:16]
		15:8	FIFODepth[15:8]
		7:0	FIFODepth[7:0]
0x011010	RNG_Control_Registers__Key0	31:24	Key0[31:24]
		23:16	Key0[23:16]
		15:8	Key0[15:8]
		7:0	Key0[7:0]
0x011014	RNG_Control_Registers__Key1	31:24	Key1[31:24]
		23:16	Key1[23:16]
		15:8	Key1[15:8]
		7:0	Key1[7:0]
0x011018	RNG_Control_Registers__Key2	31:24	Key2[31:24]
		23:16	Key2[23:16]
		15:8	Key2[15:8]
		7:0	Key2[7:0]
0x01101C	RNG_Control_Registers__Key3	31:24	Key3[31:24]
		23:16	Key3[23:16]
		15:8	Key3[15:8]
		7:0	Key3[7:0]
0x011020	RNG_Control_Registers__TestData	31:24	TestData[31:24]
		23:16	TestData[23:16]
		15:8	TestData[15:8]
		7:0	TestData[7:0]
0x011024	RNG_Control_Registers__RepeatThreshold	31:24
		23:16
		15:8
		7:0			RepeatThreshold[5:0]
0x011028	RNG_Control_Registers__PropThreshold	31:24
		23:16
		15:8							PropThreshold[9:8]
		7:0	PropThreshold[7:0]
0x01102C ... 0x01102F	Reserved
0x011030	RNG_Control_Registers__Status	31:24
		23:16
		15:8					FifoAccFail	StartUpFail	AlmInt	PreInt
		7:0	FullInt		PropFail	RepFail	State[2:0]			TestDataBusy
0x011034	RNG_Control_Registers__InitWaitVal	31:24
		23:16
		15:8	InitWaitVal[15:8]
		7:0	InitWaitVal[7:0]
0x011038	RNG_Control_Registers__DisableOsc0	31:24	DisableOsc0[31:24]
		23:16	DisableOsc0[23:16]
		15:8	DisableOsc0[15:8]
		7:0	DisableOsc0[7:0]
0x01103C	RNG_Control_Registers__DisableOsc1	31:24	DisableOsc1[31:24]
		23:16	DisableOsc1[23:16]
		15:8	DisableOsc1[15:8]
		7:0	DisableOsc1[7:0]
0x011040	RNG_Control_Registers__SwOffTmrVal	31:24
		23:16
		15:8	SwOffTmrVal[15:8]
		7:0	SwOffTmrVal[7:0]
0x011044	RNG_Control_Registers__ClkDiv	31:24
		23:16
		15:8
		7:0	ClkDiv[7:0]
0x011048	RNG_Control_Registers__AIS31Conf0	31:24	OnlineThreshold[15:8]
		23:16	OnlineThreshold[7:0]
		15:8	StartUpThreshold[15:8]
		7:0	StartUpThreshold[7:0]
0x01104C	RNG_Control_Registers__AIS31Conf1	31:24	HExpectedValue[15:8]
		23:16	HExpectedValue[7:0]
		15:8	OnlineRepThreshold[15:8]
		7:0	OnlineRepThreshold[7:0]
0x011050	RNG_Control_Registers__AIS31Conf2	31:24	HMax[15:8]
		23:16	HMax[7:0]
		15:8	HMin[15:8]
		7:0	HMin[7:0]
0x011054	RNG_Control_Registers__AIS31Status	31:24
		23:16							PrelimNoiseAlarmRep	PrelimNoiseAlarmRng
		15:8	NumPrelimAlarms[15:8]
		7:0	NumPrelimAlarms[7:0]
0x011058	RNG_Control_Registers__HwConfig	31:24
		23:16
		15:8							AIS31Full	AIS31
		7:0	NumbOfRings[7:0]
0x01105C ... 0x011FFF	Reserved
0x012000	PK_Registers__Pointers	31:24					OpPtrN[3:0]
		23:16					OpPtrC[3:0]
		15:8					OpPtrB[3:0]
		7:0					OpPtrA[3:0]
0x012004	PK_Registers__Command	31:24	CalcR2	FlagB	FlagA	SwapBytes		Edwards	RandProj	RandKE
		23:16		SelCurve[2:0]			RandMod		OpBytesM1[9:8]
		15:8	OpBytesM1[7:0]
		7:0	FieldF	OpeAddr[6:0]
0x012008	PK_Registers__Control	31:24
		23:16
		15:8
		7:0							ClearIRQ	Start
0x01200C	PK_Registers__Status	31:24				FailPtr[4:0]
		23:16							IntrptStatus	PK_Busy
		15:8	ErrorFlags[11:4]
		7:0	ErrorFlags[3:0]
0x012010 ... 0x012013	Reserved
0x012014	PK_Registers__Timer	31:24	Timer[30:23]
		23:16	Timer[22:15]
		15:8	Timer[14:7]
		7:0	Timer[6:0]
0x012018	PK_Registers__HwConfig	31:24	DisableCM	DisableClrMem	DisableSMx				AHBMaster	X25519
		23:16	P192	P521	P384	P256		ECC	BinaryField	PrimeField
		15:8	NbMult[3:0]				MaxOpSize[11:8]
		7:0	MaxOpSize[7:0]
0x01201C	PK_Registers__OpSize	31:24
		23:16
		15:8				OpSize[12:8]
		7:0	OpSize[7:0]
0x012020	PK_Registers__MemOffset	31:24	MemOffset[31:24]
		23:16	MemOffset[23:16]
		15:8	MemOffset[15:8]
		7:0	MemOffset[7:0]
0x012024	PK_Registers__MicroCodeOffset	31:24	MicroCodeOffset[31:24]
		23:16	MicroCodeOffset[23:16]
		15:8	MicroCodeOffset[15:8]
		7:0	MicroCodeOffset[7:0]