21.4.1 Principle of Operation

The GCLK_MAIN clock signal from the GCLK0 module is the source for the MCLK, which in turn is the common root for the synchronous clocks for the CPU, APB0/1/2 (Advanced Peripheral Bus), and the AHB (Advanced High-performance Bus).

For each clock domain, the CLKDIVx.DIV bitfield allows selecting a power of 2 divided clock (from 1 to 128) from the GCLK_MAIN clock, ensuring synchronous clock sources for each clock domain. The default configuration after reset and ROM code execution depends on the user configuration of BOOTCFG1/1A.MCLKDIVx registers.