20.5.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers must be synchronized when written or read.

An exception is the Channel Enable bit in the Peripheral Channel Control registers (PCHCTRLm.CHEN). When changing this bit, the bit value must be read-back to ensure the synchronization is complete (polling method) and to assert glitch free internal operation. Changing the bit value under ongoing synchronization will not generate an error.

The following registers are synchronized when written:
  • The Generic Clock Generator Control register (GENCTRLn)
  • The Control A register (CTRLA)

Required write synchronization is denoted by the “Write Synchronized” property in the register description.