21.7.4 Clock Divider Control n Register

Note:

the CLKDIV0.DIV bit field is write protected.
To ensure correct operation, frequencies must be selected so that CLKDIV0.DIV ≤ CLKDIV1.DIV ≤ CLKDIV2.DIV.
Frequencies must never exceed the specified maximum frequency for each clock domain.
The user updates to this register may not take effect immediately. The MCLK module logic will wait for the falling edge of the previous clock and the new clock to coincide before switching. The INTFLAG.CKRDY can be used to determine when MCLK has made the switch.

Table 21-6. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Bits 7:0 – DIV[7:0] These bits define the division ratio of the main clock prescaler related to the Clock Domain controlled by the CLKDIVn register. To ensure correct operation, frequencies must be selected so that FCLKDIV[n]? FCLKDIV[n+1] (i.e. CLKDIVn.DIV#CLKDIV(n+1).DIV). Frequencies must never exceed the specified maximum frequency for each clock domain. An update to this register may not take affect immediately. The MCLK macro will wait for the falling edge of the previous clock and the new clock to coincide before switching. The INTFLAG.CKRDY can be used to determine when MCLK has made the switch. This field is write protected if MCLK_CKDIV_IS_WRLOCK[n]=1. All other values are reserved.

These bits define the division ratio of the main clock, (MCLK), prescaler related to the CPU Clock Domain controlled by the CLKDIVn register.

Note: All other values are reserved or invalid.