37.15.3 LUT Control x

Note: LUTCTRLn register is Enable Protected when CCL.LUTCTRLn.ENABLE = 1.

Table 37-7. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	LUTCTRL
Offset:	0x08 + n*0x04 [n=0..7]
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	TRUTH[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
		LUTEO	LUTEI	INVEI	INSEL2[3:0]
Access		RW	RW	RW	RW	RW	RW	RW
Reset		0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	INSEL1[3:0]				INSEL0[3:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	EDGESEL		FILTSEL[1:0]				ENABLE
Access	RW		RW	RW			RW
Reset	0		0	0			0

Bits 31:24 – TRUTH[7:0] Truth Value

These bits define the value of truth logic as a function of inputs IN[2:0].

Bit 22 – LUTEO LUT Event Output Enable

Value	Name	Description
0	DISABLE	LUT event output is disabled
1	ENABLE	LUT event output is enabled

Bit 21 – LUTEI LUT Event Input Enable

Value	Name	Description
0	DISABLE	LUT incoming event is disabled
1	ENABLE	LUT incoming event is enabled

Bit 20 – INVEI Inverted Event Input Enable

Value	Name	Description
0	NORMAL	Incoming event is not inverted
1	INVERTED	Incoming event is inverted

Bits 19:16 – INSEL2[3:0] Input Selection 2

Value	Name	Description
0x0	MASK	Masked input
0x1	FEEDBACK	Feedback input source
0x2	LINK	Linked LUT input source
0x3	EVENT	Event input source
0x4	IO	I/O pin input source
0x5	PERSEL0	Peripheral 0 input source
0x6	PERSEL1	Peripheral 1 input source
0x7	PERSEL2	Peripheral 2 input source
0x8	PERSEL3	Peripheral 3 input source
0x9	PERSEL4	Peripheral 4 input source
0xA	PERSEL5	Peripheral 5 input source
0xB	ASYNCEVENT	Asynchronous event input source. The EVENT input will bypass edge detection logic.

Bits 15:12 – INSEL1[3:0] Input Selection 1

Value	Name	Description
0x0	MASK	Masked input
0x1	FEEDBACK	Feedback input source
0x2	LINK	Linked LUT input source
0x3	EVENT	Event input source
0x4	IO	I/O pin input source
0x5	PERSEL0	Peripheral 0 input source
0x6	PERSEL1	Peripheral 1 input source
0x7	PERSEL2	Peripheral 2 input source
0x8	PERSEL3	Peripheral 3 input source
0x9	PERSEL4	Peripheral 4 input source
0xA	PERSEL5	Peripheral 5 input source
0xB	ASYNCEVENT	Asynchronous event input source. The EVENT input will bypass edge detection logic.

Bits 11:8 – INSEL0[3:0] Input Selection 0

Value	Name	Description
0x0	MASK	Masked input
0x1	FEEDBACK	Feedback input source
0x2	LINK	Linked LUT input source
0x3	EVENT	Event input source
0x4	IO	I/O pin input source
0x5	PERSEL0	Peripheral 0 input source
0x6	PERSEL1	Peripheral 1 input source
0x7	PERSEL2	Peripheral 2 input source
0x8	PERSEL3	Peripheral 3 input source
0x9	PERSEL4	Peripheral 4 input source
0xA	PERSEL5	Peripheral 5 input source
0xB	ASYNCEVENT	Asynchronous event input source. The EVENT input will bypass edge detection logic.

Bit 7 – EDGESEL Edge Selection

Value	Name	Description
0	DISABLE	Edge detector is disabled
1	ENABLE	Edge detector is enabled

Bits 5:4 – FILTSEL[1:0] Filter Selection

These bits select the LUT output filter options:

Filter Selection

Value	Name	Description
0	DISABLE	Filter disabled
1	SYNCH	Synchronizer enabled
2	FILTER	Filter enabled

Bit 1 – ENABLE LUT Enable

Value	Name	Description
0	DISABLE	LUT block is disabled
1	ENABLE	LUT block is enabled

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