37.15.1 Control
Note: SEQCTRLn register is Enable-protected
when CTRL.ENABLE = 1 or LUTCTRLn.ENABLE = 1.
| Name: | CTRL |
| Offset: | 0x0 |
| Reset: | 0x00 |
| Property: | RW |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | ENABLE | SWRST | |||||||
| Access | RW | RW | W | ||||||
| Reset | 0 | 0 | 0 |
Bit 6 – RUNSTDBY Run in Standby
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | Generic clock is not required in standby sleep mode |
| 1 | ENABLE | Generic clock is required in standby sleep mode |
Bit 1 – ENABLE Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | The peripheral is disabled |
| 1 | ENABLE | The peripheral is enabled |
Bit 0 – SWRST Software Reset
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | The peripheral is not reset |
| 1 | ENABLE | The peripheral is reset |