37.15.2 SEQ Control x
Note: SEQCTRLn register is Enable-protected
when CTRL.ENABLE = 1 or LUTCTRLn.ENABLE = 1.
| Name: | SEQCTRL |
| Offset: | 0x04 + n*0x01 [n=0..3] |
| Reset: | 0x00 |
| Property: | RW |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SEQSEL[3:0] | |||||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 3:0 – SEQSEL[3:0] Sequential Selection
These bits select the sequential configuration:
Sequential Selection
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | Sequential logic is disabled |
| 1 | DFF | D flip flop |
| 2 | JK | JK flip flop |
| 3 | LATCH | D latch |
| 4 | RS | RS latch |