14.4 Peripheral Dependencies
| Peripheral Name | Base Address |
NVIC IRQ Index:Source |
MCLK AHB/APB Clock Enable Bus:Register:Bit |
GCLK Peripheral Channel Control Register |
PAC Peripheral Identifier PERID:Register:Bit |
DMA Trigger Index:Source |
Event System Type:Event: Register:Path | Power Domain |
|---|---|---|---|---|---|---|---|---|
| H2PB0 | 0x44032000 |
AHB: CLKMSK[0] MASK25 APB: CLKMSK[0] MASK26 | --- |
19 STATUS0 PERID19 |
PD_CORE_SW | |||
| H2PB1 | 0x44838000 |
AHB: CLKMSK[1] MASK25 APB: CLKMSK[1] MASK26 | --- |
46 STATUS1 PERID14 |
PD_CORE_SW | |||
| H2PB2 | 0x4500E000 |
AHB: CLKMSK[1] MASK27 APB: CLKMSK[1] MASK28 | --- |
47 STATUS1 PERID15 |
PD_CORE_SW |