39.5.12 Comparator Output Delay

The analog comparator output can be delayed by n-cycles of the control clock by using the calibration counter n-cycle values in the CMPOUCFGn register. The user has the ability to disable or re-enable this delay if desired in the COMPCTRL0n and COMPCTRL1k registers, but cannot write over the calibration values provided in the CMPOUCFGn register.

If single shot mode and output delay logic is enabled, the single comparison output will be delayed by n clock cycles(CMPOUCFGn.DLTCNT).

Figure 39-11. Comparator Output Delay Example

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