24.8.3 Config A Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CFGA |
| Offset: | 0x02 |
| Reset: | 0x0000 |
| Property: | RW |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DIVREF | MSRSEL[2:0] | ||||||||
| Access | RW | RW | RW | RW | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| REFNUM[7:0] | |||||||||
| Access | RW | RW | RW | RW | RW | RW | RW | RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 15 – DIVREF Divide Reference Clock
Divides the reference clock by 8
| Value | Name | Description |
|---|---|---|
| 0x0 | DIV1 | The reference clock is divided by 1 |
| 0x1 | DIV8 | The reference clock is divided by 8 |
Bits 10:8 – MSRSEL[2:0] Measurement Clock Selection
| Value | Name | Description |
|---|---|---|
| 0x0 | GCLK | GCLK Input Clock |
| 0x1 | CPU | CPU Input Clock |
Bits 7:0 – REFNUM[7:0] Number of Reference Clock Cycles
Selects the duration of a measurement in number of CLK_FREQM_REF cycles.