35.5.10 Sleep Mode Operation

The CAN module can be configured to operate in any idle sleep mode if both AHB and GCLK clocks are available. The CAN interrupts can be used to wake up the device from sleep mode.

The CAN module has its own low power mode that may be used at any time without disabling this module. This is performed by writing one to the Clock Stop Request bit in the CC Control register (CCCR.CSR bit (CCCR <4>) = 1). Once all pending transactions are completed and the idle bus state is detected, the CAN will automatically set the Clock Stop Acknowledge bit (CCCR.CSA bit (CCCR <3>) = 1). The CAN then reverts back to its initial state (CCCR.INIT bit (CCCR <0>) = 1), blocking further transfers.

To exit low power mode, CCCR.CSR bit (CCCR<4>) in CCCR register must be written to 0. Afterwards, the application can restart CAN communication by resetting bit CCCR.INIT bit (CCCR <0>).

After reset, the GCLK_CANx and CLK_CANx_AHB clocks are not requested, except for each APB bus access. However, after the CAN initialization, both GCLK_CANx and CLK_CANx_AHB clocks are requested as long as Clock Stop Request bit in the CC Control register is cleared (CCCR.CSR (CCCR<4>)= 0), and stopped when Clock Stop Request bit in the CC Control register is set (CCCR.CSR (CCCR<4>) = 1) and the Clock Stop Acknowledge bit is set (CCCR.CSA (CCCR<3>)= 1). To limit the wake-up time latency, the CAN clock sources must be enabled in continuous mode (ONDEMAND of respective oscillator must be set zero). For further details, refer to the Clock System chapter.

In Standby sleep mode, when the RUNSTDBY bit is set (CTRLA.RUNSTDBY=1), the CAN IP is allowed to continue to run its operation.

When the RUNSTDBY bit is cleared (CTRLA.RUNSTDBY=0) and the Standby sleep mode is detected, a hardware mechanism will request the CAN peripheral to stop its operation, and enables the CAN low power mode automatically. The CCCR.CSR bit is automatically set to one as long as the stop request operation is active.

When all pending transmission requests have completed, the CAN waits until bus idle state is detected. Then the CAN sets the CCCR.INIT to one to prevent any further CAN transfers. The hardware stop request is acknowledged and the CCCR.CSA bit is set one. The clocks requests are switched off.

When the system exits the Standby sleep mode, CSR bit in CCCR register must be written to 0. Afterward, the application can restart CAN communication by resetting bit CCCR.INIT.

Note: In case of a heavily disturbed CAN bus, it may happen that an idle state is never reached and CCCR.INIT is therefore not set by the CAN. This situation can be detected by polling PSR.ACT. In case there is a risk the CAN does not enter idle state, it is recommended to use the software procedure to put the CAN in low power mode, before the system goes to Standby sleep mode. In this way, the software can write CCCR.INIT = ‘1’, which stops CAN communication immediately, regardless whether there is a transmission or reception ongoing or not.