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32-bit Arm Cortex-M23 Low Power MCU with Security, Safety, CAN-FD, Full Speed USB, Touch and Advanced Analog
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PIC32CM5112GC00048
PIC32CM5112GC00064
PIC32CM5112GC00100
PIC32CM5112SG00048
PIC32CM5112SG00064
PIC32CM5112SG00100
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35
Controller Area Network (CAN)
35.5
Functional Description
35.5.2
Operating Modes
32-bit Arm® Cortex®-M23 MCU with Security, Functional Safety (FuSa), CAN-FD, Full-Speed USB, Enhanced Touch, and Advanced Analog
1
Guidelines for Getting Started
2
Configuration Summary
3
Ordering Information
4
Block Diagram
5
Pinout and Packaging
6
Signal Description
7
Power Supplies and Startup Considerations
8
Product Mapping
9
Peripherals
10
Processor and Architecture
11
Memories
12
PIC32CM SG00/GC00
Security Features
13
Implementation Defined Attribution Unit (IDAU)
14
System Bus AHB - APB Bridge (H2PB)
15
Multi-Channel RAM Controller (MCRAMC)
16
Peripheral Access Controller (PAC)
17
Device Service Unit (DSU)
18
Clock Distribution System
19
Oscillator Controller (OSCCTRL)
20
Generic Clock Controller (GCLK)
21
Main Clock (MCLK)
22
32 KHz Oscillators Controller (OSC32KCTRL)
23
Watchdog Timer (WDT)
24
Frequency Meter (FREQM)
25
Real-Time Counter (RTC)
26
Direct Memory Access Controller (DMAC)
27
Supply Controller (SUPC)
28
Power Manager (PM)
29
Reset Controller (RSTC)
30
External Interrupt Controller (EIC)
31
Non-Volatile Memory Controller (NVMCTRL)
32
Event System (EVSYS)
33
I/O Pin Controller (PORT)
34
Serial Communication Interface (SERCOM)
35
Controller Area Network (CAN)
35.1
Overview
35.2
Features
35.3
Block Diagram
35.4
Signal Description
35.5
Functional Description
35.5.1
Principle of Operation
35.5.2
Operating Modes
35.5.2.1
Software Initialization
35.5.2.2
Normal Operation
35.5.2.3
CAN FD Operation
35.5.2.4
Transceiver Delay Compensation
35.5.2.5
Restricted Operation Mode
35.5.2.6
Bus Monitoring Mode
35.5.2.7
Disabled Automatic Retransmission
35.5.2.8
Test Modes
35.5.3
Timestamp Generation
35.5.4
Timeout Counter
35.5.5
Rx Handling
35.5.6
Tx Handling
35.5.7
FIFO Acknowledge Handling
35.5.8
Message RAM
35.5.9
Interrupts
35.5.10
Sleep Mode Operation
35.5.11
Synchronization
35.6
Peripheral Dependencies
35.7
Register Summary
35
Rx Buffer and FIFO Element Register Summary
35
Tx Buffer Element Register Summary
35
Tx Event FIFO Element Register Summary
35
Standard Message ID Filter Element Register Summary
35
Extended Message ID Filter Element Register Summary
36
Universal Serial Bus (USB)
37
Configurable Custom Logic (CCL)
38
Analog to Digital Converter (ADC)
39
Analog Comparator (AC)
40
Timer/Counter for Control Applications (TCC)
41
TrustRAM (TRAM)
42
Peripheral Touch Controller (PTC)
43
Hardware Security Module Lite (HSM-Lite)
44
Anti-Tamper Module (AT)
45
Physically Uncloneable Function (PUF)
46
Electrical Characteristics
47
Packaging Information
48
Schematic Checklist
49
Common Conventions
50
Acronyms and Abbreviations
51
Revision History
Microchip Information
35.5.2 Operating Modes
