35.5.9 Interrupts

The CAN has the following interrupt sources, which can be assigned to 2 interrupt lines:

  • Access to Reserved Address
  • Protocol Errors (Data Phase / Arbitration Phase)
  • Watchdog Interrupt
  • “bus off” Status
  • Error Warning & Passive
  • Error Logging Overflow
  • Message stored to Dedicated Rx Buffer
  • Timeout Occurred
  • Message RAM Access Failure
  • Timestamp Wraparound
  • Tx Event FIFO statuses (Element Lost / Full / Watermark Reached / New Entry)
  • Tx FIFO Empty
  • Transmission Cancellation Finished
  • Timestamp Completed
  • High Priority Message
  • Rx FIFO 1 Statuses (Message Lost / Full / Watermark Reached / New Message)
  • Rx FIFO 0 Statuses (Message Lost / Full / Watermark Reached / New Message)

Each interrupt source has an interrupt flag associated with it. The interrupt flag register (IR) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing ‘1’ or disabled by writing ‘0’ to the corresponding bit in the interrupt enable register (IE). Each interrupt flag can be assigned to one of two interrupt service lines.

An interrupt request is generated when an interrupt flag is set, the corresponding interrupt enable is set, and the corresponding service line enable assigned to the interrupt is set. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, the service line is disabled, or the CAN is reset. Refer to the IR register for details on how to clear interrupt flags. The interrupt request lines are connected to the Nested Vector Interrupt Controller (NVIC). All interrupt requests from the peripheral are sent to the Nested vector Interrupt Controller NVIC. Using the CAN FD interrupt requires the interrupt controller to be configured first. The user must read the IR register to determine which interrupt condition is present.

The CAN also has two other interrupt sources:

  • AHB Bus Error (BERR)
  • Debug Message Reception Interrupt (DBG)

These two interrupt lines have dedicated bit in the INTFLAG register. The user must read the INTFLAG register to determine which interrupt condition is present.

The interrupt source can be enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). The interrupt request is generated when the interrupt flags is set, and the interrupt is enabled. The interrupt request remains active until the interrupt flags source of interrupt is cleared, or when the interrupt source is disabled. Refer to INTFLAG register for details on how to clear interrupt flags.

The interrupt flags are cleared in the case of a hardware reset condition detection.

Note: Interrupts must be globally enabled for interrupt requests to be generated.