36.8.8 End Point Interrupt Summary
| Name: | EPINTSMRY |
| Offset: | 0x020 |
| Reset: | 0x0000 |
| Property: | R |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EPINT[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EPINT[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – EPINT[15:0] End Point x Interrupt
The flag EPINT[n] is set when an interrupt is triggered by the EndPoint n.
This bit will be cleared when no interrupts are pending for EndPoint n.