34.6.2 Features

SERCOM SPI includes the following features:

  • Full-duplex, four-wire interface (MISO, MOSI, SCK, SS)
  • One-level transmit buffer, two-level receive buffer
  • Supports all four SPI modes of operation
  • Single data direction operation allows alternate function on the MISO or MOSI pin
  • Selectable LSB or MSB-first data transfer
  • Can be used with DMA
  • 0-bit Extension for better system bus utilization
  • Framed SPI protocol support in both Host and Client operating mode, with hardware controlled FSYNC
  • Internal FIFO (See Table below)
  • Host operation:
    • Serial clock speed, fSCK=1/tSCK1
    • 8-bit clock generator
    • Hardware controlled SS
    • Optional inter-character spacing
  • Client Operation:
    • Serial clock speed, fSCK=1/tSSCK1
    • Optional 8-bit address match operation
    • Operation in all sleep modes
    • Wake on SS transition
Note:
  1. For tSCK and tSSCK values, refer to SPI Timing Characteristics.
Table 34-9. FIFO Buffer Configuration
FIFO StatusTransmit Buffer(s)Receive Buffer(s)

Disabled or

Not Implemented

Single write buffer.A two-level receive buffer.
Enabled0 write FIFO buffer.0 receive FIFO buffer.

In addition, the SPI Host uses the SERCOM baud-rate generator, while the SPI Client can use the SERCOM address match logic.