34.11.5 Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). On read, a bit value of zero indicates the associated interrupt is disabled while a bit value of one indicates the associated interrupt is enabled.
Table 34-57. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: INTENCLR
Offset: 0x14
Reset: 0x00
Property: RW

Bit 76543210 
 ERROR  RXFFTXFE SBMB 
Access RWRWRWRWRW 
Reset 00000 

Bit 7 – ERROR Combined Error Interrupt Disable

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.

Bit 4 – RXFF Rx FIFO Full Interrupt Disable

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the RX FIFO Full bit, which disables the RX FIFO Full interrupt.

Bit 3 – TXFE Tx FIFO Empty Interrupt Disable

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the TX FIFO Empty bit, which disables the TX FIFO Empty interrupt.

Bit 1 – SB Slave On Bus Interrupt Disable

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the Client on Bus Interrupt Enable bit, which disables the Client on Bus interrupt.

ValueDescription
0The Client on Bus interrupt is disabled.
1The Client on Bus interrupt is enabled.

Bit 0 – MB Master On Bus Interrupt Disable

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the Host on Bus Interrupt Enable bit, which disables the Host on Bus interrupt.

ValueDescription
0The Host on Bus interrupt is disabled.
1The Host on Bus interrupt is enabled.