26.6.10 Priority Control 1

Table 26-3. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	PRICTRL1
Offset:	0x18
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	RRLVLEN7			LVLPRI7[4:0]
Access	RW			RW	RW	RW	RW	RW
Reset	0			0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	RRLVLEN6			LVLPRI6[4:0]
Access	RW			RW	RW	RW	RW	RW
Reset	0			0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	RRLVLEN5			LVLPRI5[4:0]
Access	RW			RW	RW	RW	RW	RW
Reset	0			0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	RRLVLEN4			LVLPRI4[4:0]
Access	RW			RW	RW	RW	RW	RW
Reset	0			0	0	0	0	0

Bit 31 – RRLVLEN7 Level 7 Round-Robin Scheduling Enable

Bits 28:24 – LVLPRI7[4:0] Level 7 Channel Priority Number

Bit 23 – RRLVLEN6 Level 6 Round-Robin Scheduling Enable

Bits 20:16 – LVLPRI6[4:0] Level 6 Channel Priority Number

Bit 15 – RRLVLEN5 Level 5 Round-Robin Scheduling Enable

Bits 12:8 – LVLPRI5[4:0] Level 5 Channel Priority Number

Bit 7 – RRLVLEN4 Level 4 Round-Robin Scheduling Enable

Bits 4:0 – LVLPRI4[4:0] Level 4 Channel Priority Number

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.