25.8.1 Control A

Table 25-15. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CTRLA
Offset:	0x00
Reset:	0x0000
Property:	RW


Bit	15	14	13	12	11	10	9	8
	COUNTSYNC	GPTRST	BKTRST		PRESCALER[3:0]
Access	RW	RW	RW		RW	RW	RW	RW
Reset	0	0	0		0	0	0	0


Bit	7	6	5	4	3	2	1	0
					MODE[1:0]		ENABLE	SWRST
Access					RW	RW	RW	W
Reset					0	0	0	0

Bit 15 – COUNTSYNC Count Read Synchronization Enable

The COUNT register requires synchronization when reading. Disabling the synchronization will prevent reading valid values from the COUNT register.

This bit is not enable-protected.

Value	Description
0	COUNT read synchronization is disabled
1	COUNT read synchronization is enabled

Bit 14 – GPTRST GP Registers Reset On Tamper Enable

Only GP registers enabled by the CTRLB.GPnEN bits are affected. This bit can be written only when the peripheral is disabled.

This bit is not synchronized.

Value	Description
0	GPn registers will not reset when a tamper condition occurs.
1	GPn registers will reset when a tamper condition occurs.

Bit 13 – BKTRST BKUP Registers Reset On Tamper Enable

Bits 11:8 – PRESCALER[3:0] Prescaler

These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized.

Value	Name	Description
0	OFF	CLK_RTC_CNT = GCLK_RTC/1
0xA	DIV512	CLK_RTC_CNT = GCLK_RTC/512
0xB	DIV1024	CLK_RTC_CNT = GCLK_RTC/1024
1	DIV1	CLK_RTC_CNT = GCLK_RTC/1
2	DIV2	CLK_RTC_CNT = GCLK_RTC/2
3	DIV4	CLK_RTC_CNT = GCLK_RTC/4
4	DIV8	CLK_RTC_CNT = GCLK_RTC/8
5	DIV16	CLK_RTC_CNT = GCLK_RTC/16
6	DIV32	CLK_RTC_CNT = GCLK_RTC/32
7	DIV64	CLK_RTC_CNT = GCLK_RTC/64
8	DIV128	CLK_RTC_CNT = GCLK_RTC/128
9	DIV256	CLK_RTC_CNT = GCLK_RTC/256

Bits 3:2 – MODE[1:0] Operating Mode

This field defines the operating mode of the RTC. This bit is not synchronized.

Value	Name	Description
0	COUNT32	Mode 0: 32-bit Counter
1	COUNT16	Mode 1: 16-bit Counter
2	CLOCK	Mode 2: Clock/Calendar

Bit 1 – ENABLE Enable

Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.

This bit is not enable-protected.

Value	Description
0	The peripheral is disabled
1	The peripheral is enabled

Bit 0 – SWRST Software Reset

Writing a '0' to this bit has no effect.

Writing a '1' to this bit resets all registers in the RTC (except DBGCTRL) to their initial state, and the RTC will be disabled.

Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.

Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST will be cleared when the reset is complete.

This bit is not enable-protected.

Value	Description
0	There is not reset operation ongoing
1	The reset operation is ongoing