16.7.6 Interrupt Flag n Register

This flag is set when an access error is detected by the CLIENT n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.

Note:
  1. Not available on 100-pin packages
  2. Not available on 100-pin and 144-pin packages
  3. Not available on 100-pin, 144-pin, and 176-pin packages
Table 16-7. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: INTFLAG
Offset: 0x20 + n*0x04 [n=0..3]
Reset: 0x00000000
Property: R/K

Bit 3130292827262524 
 PERID31PERID30PERID29PERID28PERID27PERID26PERID25PERID24 
Access R/K/HSR/K/HSR/K/HSR/K/HSR/K/HSR/K/HSR/K/HSR/K/HS 
Reset 00000000 
Bit 2322212019181716 
 PERID23PERID22PERID21PERID20PERID19PERID18PERID17PERID16 
Access R/K/HSR/K/HSR/K/HSR/K/HSR/K/HSR/K/HSR/K/HSR/K/HS 
Reset 00000000 
Bit 15141312111098 
 PERID15PERID14PERID13PERID12PERID11PERID10PERID9PERID8 
Access R/K/HSR/K/HSR/K/HSR/K/HSR/K/HSR/K/HSR/K/HSR/K/HS 
Reset 00000000 
Bit 76543210 
 PERID7PERID6PERID5PERID4PERID3PERID2PERID1PERID0 
Access R/K/HSR/K/HSR/K/HSR/K/HSR/K/HSR/K/HSR/K/HSR/K/HS 
Reset 00000000 

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – PERID This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAG bit, and generates an interrupt request if INTENCLR/SET.ERR is one. Read value reflects the state of the interrupt flag.

ValueNameDescription
1Interrupt pending
0Interrupt not pending