This flag is set when an access error is
detected by the CLIENT n, and will generate an interrupt request if INTENCLR/SET.ERR is
'1'.
Writing a '0' to this bit has no
effect.
Writing a '1' to this bit will clear the
corresponding INTFLAGAHB interrupt flag.
Note:
Not available on 100-pin
packages
Not available on 100-pin and
144-pin packages
Not available on 100-pin, 144-pin,
and 176-pin packages
Table 16-7. Register Bit Attribute
Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable bit
HC
Cleared by Hardware
(Grey cell)
Unimplemented
W
Writable bit
HS
Set by Hardware
X
Bit is unknown at Reset
K
Write to clear
S
Software settable bit
—
—
Name:
INTFLAG
Offset:
0x20 + n*0x04 [n=0..3]
Reset:
0x00000000
Property:
R/K
Bit
31
30
29
28
27
26
25
24
PERID31
PERID30
PERID29
PERID28
PERID27
PERID26
PERID25
PERID24
Access
R/K/HS
R/K/HS
R/K/HS
R/K/HS
R/K/HS
R/K/HS
R/K/HS
R/K/HS
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
PERID23
PERID22
PERID21
PERID20
PERID19
PERID18
PERID17
PERID16
Access
R/K/HS
R/K/HS
R/K/HS
R/K/HS
R/K/HS
R/K/HS
R/K/HS
R/K/HS
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
PERID15
PERID14
PERID13
PERID12
PERID11
PERID10
PERID9
PERID8
Access
R/K/HS
R/K/HS
R/K/HS
R/K/HS
R/K/HS
R/K/HS
R/K/HS
R/K/HS
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PERID7
PERID6
PERID5
PERID4
PERID3
PERID2
PERID1
PERID0
Access
R/K/HS
R/K/HS
R/K/HS
R/K/HS
R/K/HS
R/K/HS
R/K/HS
R/K/HS
Reset
0
0
0
0
0
0
0
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – PERID This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAG bit, and generates an interrupt request if INTENCLR/SET.ERR is one.
Read value reflects the state of the interrupt flag.
Value
Name
Description
1
Interrupt pending
0
Interrupt not pending
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