42.6.2.2 Enabling, Disabling and Resetting

The PTC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The PTC is disabled by writing CTRLA.ENABLE=0.

To go to the active mode from the off mode, the application must wait for the bias generators to stabilize, this wait is specified in powers of 2 by the exponent bit field CTRLA.WKUPEXP[3:0]. The bit field CTRLA.WKUPEXP[3:0] generates the full count 2WKUPEXP, (where WKUPEXP is mapped internally to be always 4 or greater), which controls how many PTC core clocks are needed in the PTC core to fully power-up the analog bias circuitry. This delay is enforced every time CTRLA.ENABLE has a low to high transition. During this delay, the triggers are blocked from starting conversions, because the analog core is not ready yet. At the end of the delay, the corresponding status bit ACRRDY is set in the INTFLAG register for the user to poll and determine when the PTC Core is ready for operation and the triggers are allowed to start conversions. Because the delays are significant, the ACRRDY status bits can be enabled as part of an group interrupt request.

The PTC is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the PTC, except DBGCTRL, will be reset to their initial state, and the PTC will be disabled. Refer to CTRLA for details.