25.3.3.2.1 Clock Recovery

Since there is no common clock signal in Asynchronous mode, each communicating device generates separate clock signals. These clock signals must be configured to run at the same baud rate for communication to occur. The devices, therefore, run at the same speed, but their timing is skewed in relation to each other. To accommodate this, the USART features a hardware clock recovery unit that synchronizes incoming asynchronous serial frames with the internally generated baud rate clock.

The figure below illustrates the sampling process for the Start bit of an incoming frame, showing the timing scheme for both Normal and Double-Speed mode. These modes are selected by configuring the Sample Rate (SAMPR) bit in the Control C (USARTn.CTRLC) register. The sample rate for Normal mode is 16 times the baud rate, while the sample rate for Double-Speed mode is eight times the baud rate (see Double-Speed Operation for more details). The horizontal arrows indicate the maximum synchronization error. Note that the maximum synchronization error is larger in Double-Speed mode.

When the clock recovery logic detects a falling edge from the Idle (high) state to the Start bit (low), the Start bit detection sequence is initiated. In the figure above, sample 1 denotes the first sample reading ‘0’. The clock recovery logic then uses three subsequent samples (samples 8, 9, and 10 in Normal mode, and samples 4, 5, 6 in Double-Speed mode) to decide if a valid Start bit is received. If two or three samples read ‘0’, the Start bit is accepted, the clock recovery unit is synchronized, and the data recovery can begin. If less than two samples read ‘0’, the Start bit is rejected. This process is repeated for each Start bit.