25.3.3.2.2 Data Recovery

Similar to clock recovery, the data recovery unit samples at a rate 8 or 16 times faster than the baud rate, depending on whether it is running in Double-Speed or Normal mode, respectively. The figure below illustrates the sampling process for reading a bit in a received frame.

Figure 25-7. Sampling of Data and Parity Bits

A majority voting technique is, similar to that used in clock recovery, is applied to the three center samples to determine the logic level of each received bit. This process is repeated for each bit until a complete frame is received.

The data recovery unit receives only the first Stop bit and ignores any additional Stop bits. If the sampled Stop bit is read ‘0’, the Frame Error flag will be set. The figure below illustrates the sampling of a Stop bit and shows the earliest possible beginning of the next frame’s Start bit.

Figure 25-8. Stop Bit and Next Start Bit Sampling

A new high-to-low transition, indicating the Start bit of a new frame, can come right after the last of the bits used for majority voting. For Normal-Speed mode, the first low-level sample can appear at point (A) in the figure above. For Double-Speed mode, the first low-level sample must be delayed to point (B), which is the first sample after the majority vote samples. Point (C) marks a Stop bit of full length at the nominal baud rate.