25.3.4.7 Hardware Handshake

The USART features an out-of-band hardware handshaking mechanism, separate from the communication lines, to control transmission flow.

Figure 25-21. Hardware Handshake Connection

Hardware handshake is enabled by configuring the Communication Signals (CSIG) field in the Control A (USARTn.CTRLA) register to 0x02 (HANDSHAKE). Communication Mode (CMODE) in CTRLA must be configured to 0x00 (ASYNCHRONOUS).

The receiver drives its RTS pin high when it is unable to receive data, either because the receive buffers are full, or the receiver is disabled. This indicates to the remote device that it must stop transmitting after the ongoing transmission is complete, avoiding buffer overflow or lost data. The incoming data is stored in the shift register until the receive buffer is no longer full.

Figure 25-22. Receiver Behavior with Hardware Handshake

The transmitter automatically stops transmitting a new frame if the CTS pin is read as high. The current CTS level can be checked in the Status (USARTn.STATUS) register. When CTS changes from low to high, the transmitter will finish the ongoing transmission and then stop.

The figure below illustrates the transmitter behavior based on the state of the CTS pin.

Figure 25-23. Transmitter Behavior with Hardware Handshake