8.3 Sequential Read

Sequential reads are initiated by either a current address read or a random read. After the bus host receives a data word, it responds with an Acknowledge. As long as the EEPROM receives an ACK, it will continue to increment the word address and serially clock out sequential data words. When the maximum memory address is reached, the data word address will roll over and the sequential read will continue from the beginning of the memory array. All types of read operations will be terminated if the bus host does not respond with an ACK (it NACKs) during the ninth clock cycle. After the NACK response, the host may send a Stop condition to complete the protocol, or it can send a Start condition to begin the next sequence.

Figure 8-3. Sequential Read
Note:
  1. For the AT24C01C, AT24C02C and AT24C04C, the @ indicates the A1 hardware client address bit. For the AT24C08C, the @ indicates the A9 word address bit.
  2. For the AT24C01C and AT24C02C, the $ indicates the A0 hardware client address bit. For the AT24C04C and AT24C08C, the $ indicates the A8 word address bit.