8.2 Random Read

A random read begins in the same way as a byte write operation does to load in a new data word address. This is known as a “dummy write” sequence; however, the data byte and the Stop condition of the byte write must be omitted to prevent the part from entering an internal write cycle. Once the device address and word address are clocked in and acknowledged by the EEPROM, the bus host must generate another Start condition. The bus host now initiates a current address read by sending a Start condition, followed by a valid device address byte with the R/W bit set to logic ‘1’. In this second device address byte for the AT24C04C and AT24C08C, the bit positions usually reserved for the Most Significant bits of the word address (bit 1 for AT24C04C and bits 2 and 1 for AT24C08C) are "don't care" bits since the address that will be read from is determined only by what was sent in the dummy write portion of the sequence. The EEPROM will ACK the device address and serially clock out the data word on the SDA line. All types of read operations will be terminated if the bus host does not respond with an ACK (it NACKs) during the ninth clock cycle. After the NACK response, the host may send a Stop condition to complete the protocol, or it can send a Start condition to begin the next sequence.