8.3 Writing to the Write Protection Register

When writing the WPR, data bit 7 through 4 are used to ensure that a write operation was intentional. For all write operations to the WPR, bit 6 must be a logic ‘1’ as seen in Table 8-4.

Additionally, data bit 5 must be set in accordance with the D0 bit value (WPRL) as noted below. If the WPR is to remain unlocked, then the upper nibble sent during the write operation would be 4h and D0 must be a logic ‘0’, whereas if the WPR is to be permanently locked, the upper nibble would need to be 6h and D0 must be a logic ‘1’. A mismatch of D5 and the WPRL bit will cause the write cycle to abort.

Sending more than one byte to the AT24CSW01X/AT24CSW02X when trying to write to the WPR will cause the write cycle to abort and the contents of the WPR will not be changed. Additionally, if the WPR is already locked (WPRL = 1), the write cycle will not execute and the device will be ready for a new operation.