32.11.3 Non-Maskable Interrupt Flag Status and Clear
Important: Devices where the EIC is configured as Mix-Secure,
read and write accesses are allowed only if the NMI interrupt is set as Non-Secure
in the NONSEC register (NONSEC.NMI bit).
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | NMIFLAG |
| Offset: | 0x02 |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NMI | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – NMI Non-Maskable Interrupt
This flag is cleared by writing a '1' to it.
This flag is set when the NMI pin matches the NMI sense configuration and will generate an interrupt request.
Writing a '0' to this bit has no effect.