27.8 Register Summary - MODE0


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	CTRLA	7:0	MATCHCLR				MODE[1:0]		ENABLE	SWRST
0x00	CTRLA	15:8	COUNTSYNC	GPTRST	BKTRST		PRESCALER[3:0]
0x02	CTRLB	7:0	DMAEN	RTCOUT	DEBASYNC	DEBMAJ			GP2EN	GP0EN
0x02	CTRLB	15:8	SEPTO	ACTF[2:0]				DEBF[2:0]
0x04	EVCTRL	7:0	PEREO7	PEREO6	PEREO5	PEREO4	PEREO3	PEREO2	PEREO1	PEREO0
		15:8	OVFEO	TAMPEREO					CMPEO[1:0]
		23:16								TAMPEVEI
		31:24								PERDEO
0x08	INTENCLR	7:0	PER7	PER6	PER5	PER4	PER3	PER2	PER1	PER0
0x08	INTENCLR	15:8	OVF	TAMPER					CMP1	CMP0
0x0A	INTENSET	7:0	PER7	PER6	PER5	PER4	PER3	PER2	PER1	PER0
0x0A	INTENSET	15:8	OVF	TAMPER					CMP1	CMP0
0x0C	INTFLAG	7:0	PER7	PER6	PER5	PER4	PER3	PER2	PER1	PER0
0x0C	INTFLAG	15:8	OVF	TAMPER					CMP1	CMP0
0x0E ... 0x0F	Reserved
0x10	SYNCBUSY	7:0		COMP1	COMP0		COUNT	FREQCORR	ENABLE	SWRST
		15:8	COUNTSYNC
		23:16					G3	G2	G1	G0
		31:24
0x14 ... 0x17	Reserved
0x18	COUNT	7:0	COUNT[7:0]
		15:8	COUNT[15:8]
		23:16	COUNT[23:16]
		31:24	COUNT[31:24]
0x1C ... 0x1F	Reserved
0x20	COMP	7:0	COMP[7:0]
		15:8	COMP[15:8]
		23:16	COMP[23:16]
		31:24	COMP[31:24]
0x24	COMP	7:0	COMP[7:0]
		15:8	COMP[15:8]
		23:16	COMP[23:16]
		31:24	COMP[31:24]
0x28 ... 0x63	Reserved
0x64	TIMESTAMP	7:0	COUNT[7:0]
		15:8	COUNT[15:8]
		23:16	COUNT[23:16]
		31:24	COUNT[31:24]