27.8.7 Synchronization Busy Status

Table 27-11. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: R

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     G3G2G1G0 
Access RRRR 
Reset 0000 
Bit 15141312111098 
 COUNTSYNC        
Access R 
Reset 0 
Bit 76543210 
  COMP1COMP0 COUNTFREQCORRENABLESWRST 
Access RRRRRR 
Reset 000000 

Bits 16, 17, 18, 19 – GP General Purpose x Register Busy

ValueDescription
0Write synchronization for GPn register is complete.
1Write synchronization for GPn register is ongoing.

Bit 15 – COUNTSYNC Count Synchronization Enable Bit Busy

ValueDescription
0Write synchronization for the CTRLA.COUNTSYNC bit is complete.
1Write synchronization for the CTRLA.COUNTSYNC bit is ongoing.

Bits 5, 6 – COMPn Compare n Synchronization Busy Status [n = 1..0]

ValueDescription
0Write synchronization for COMPx register is complete.
1Write synchronization for COMPx register is ongoing.

Bit 3 – COUNT COUNT Register Busy

ValueDescription
0Read/write synchronization for the COUNT register is complete.
1Read/write synchronization for the COUNT register is ongoing.

Bit 2 – FREQCORR FREQCORR Register Busy

ValueDescription
0Write synchronization for the FREQCORR register is complete.
1Write synchronization for the FREQCORR register is ongoing.

Bit 1 – ENABLE Enable Bit Busy

ValueDescription
0Write synchronization for the CTRLA.ENABLE bit is complete.
1Write synchronization for the CTRLA.ENABLE bit is ongoing.

Bit 0 – SWRST Software Reset Busy

ValueDescription
0Write synchronization for the CTRLA.SWRST bit is complete.
1Write synchronization for the CTRLA.SWRST bit is ongoing.