42.5.2.2 Initialization

The following registers are enable-protected, meaning that they can only be written when TCC is disabled (CTRLA.ENABLE = 0):
  • The Recoverable Fault Control registers (FCTRLA and FCTRLB)
  • The Waveform Extension Control register (WEXCTRL)
  • The Drive Control register (DRVCTRL)
  • The Event Control register (EVCTRL)

Register Enable-protection is denoted by the Enable-Protected property in the register description.

The following register bits are enable-protected, meaning that they can only be written when the TCC is disabled (CTRLA.ENABLE = 0):

  • The Capture Channel x Enable bits in the Control A register (CTRLA.CPTEN[31:24])
  • DMA One-shot Trigger Mode (CTRLA.DMAOS)
  • Full Cycle (CTRLA.FCYCLE)
  • Auto Lock (CTRLA.ALOCK)
  • Prescaler and Counter Synchronization Selection (CTRLA.PRESCSYNC)
  • Run in Standby (CTRLA.RUNSTDBY)
  • Prescaler (CTRLA.PRESCALER)
  • Enhanced Resolution (CTRLA.RESOLUTION)

When the CTRLA.ENABLE bit (CTRLA <1>) is '0', the Enable-Protected bits in the CTRLA register can be written at the same time the CTRLA.ENABLE bit (CTRLA <1>) is written to '1'. However, when the CTRLA.ENABLE bit (CTRLA <1>) is '1' these bits can not be written at the same time CTRLA.ENABLE bit (CTRLA <1>) is written to '0'. the enable-protection is denoted by the Enable-Protected property in the register description.

Before TCC is enabled, it must be configured as outlined by the following steps:
  1. Configure the clock source for the TCC Instance in the Main Clock Controller (MCLK) and enable the APB BUS clock for the TCC Instance by writing a ‘1’ to the TCCx_bit in the Peripheral Bus Clock Enable Maskn Register of the MCLK module.
  2. If Capture mode is required, enable the channel in Capture mode by writing a '1' to the Capture Enable bit in the Control A register (i.e., for the Channel 0 CTRLA.CPTEN0 bit (CTRLA <24>), for the Channel 1 CTRLA.CPTEN1 bit (CTRLA <25>) and so on).
Optionally, the following configurations can be set before enabling TCC:
  1. Select PRESCALER setting in the Control A register (CTRLA.PRESCALER bits (CTRLA <10:8>)).
  2. Select Prescaler Synchronization setting in Control A register (CTRLA.PRESYNC bits (CTRLA <13:12>)).
  3. If down-counting operation is desired, write the Counter Direction bit in the Control B Set register (CTRLBSET.DIR bit (CTRLBSET <0>)) to '1'. In this case, the COUNT register must be initialized with the desired TOP value.
  4. Select the Waveform Generation operation in the WAVE register (WAVEGEN bits (WAVE <2:0>)).
  5. The output polarity for each individual channel can be changed by configuring the corresponding WAVE.POLy bit, where y = 0,1,2,..7. For example, when the CC0 register is used for the duty cycle, the corresponding WAVE.POL0 bit (WAVE<16>) decides the polarity.
  6. The waveform output for each individual channel can be inverted by configuring the corresponding Waveform Output Invert Enable DRVCTRL.INVENy bits where y = 0,1,2…7. For example, when CC0 register is used for the duty cycle, corresponding DRVCTRL.INVEN0 bit (DRVCTRL <16>) decides inversion.
Note: See different PWM modes for detailed information.