21.8.3 Interrupt Enable Set

Table 21-7. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: INTENSET
Offset: 0x08
Reset: 0x00000000
Property: RW

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).

Bit 3130292827262524 
        PLL0LOCKR 
Access RW 
Reset 0 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
   DFLLFAILDFLLRCSDFLLUNFDFLLOVFDFLLLOCKDFLLRDY 
Access RWRWRWRWRWRW 
Reset 000000 
Bit 76543210 
      CLKFAILXOSCFAILXOSCRDY 
Access RWRWRW 
Reset 000 

Bit 24 – PLL0LOCKR PLL 0 Lock Rise Interrupt Enable

Writing a zero to this bit has no effect.

Writing a '1' to this bit will set the PLL Lock Rise Interrupt Enable bit, which enables the PLL Lock Rise interrupt.

ValueDescription
0

The PLL Lock Rise interrupt is disabled

1

The PLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the PLL Lock Rise Interrupt flag is set

Bit 13 – DFLLFAIL DFLL Startup Failure Interrupt Enable

Writing a zero to this bit has no effect.

Writing a '1' to this bit will set the DFLL Startup Failure Interrupt Enable bit, which enables the DFLL Startup Failure interrupt.

ValueDescription
0The DFLL48M Startup Failure interrupt is disabled.
1The DFLL48M Startup Failure interrupt is enabled, and an interrupt request will be generated when the DFLL Startup Failure Interrupt flag is set.

Bit 12 – DFLLRCS DFLL Reference Clock Stopped Interrupt Enable

Writing a zero to this bit has no effect.

Writing a '1' to this bit will set the DFLL Reference Clock Stopped Interrupt Enable bit, which enables the DFLL Reference Clock Stopped interrupt.

ValueDescription
0The DFLL48M Reference Clock Stopped interrupt is disabled.
1The DFLL48M Reference Clock Stopped interrupt is enabled, and an interrupt request will be generated when the DFLL Reference Clock Stopped Interrupt flag is set.

Bit 11 – DFLLUNF DFLL Tuner Underflow Interrupt Enable

Writing a zero to this bit has no effect.

Writing a '1' to this bit will set the DFLL Tuner Underflow Interrupt Enable bit, which enables the DFLL Tuner Underflow interrupt.

ValueDescription
0The DFLL Tuner Underflow interrupt is disabled.
1The DFLL Tuner Underflow interrupt is enabled, and an interrupt request will be generated when the DFLL Tuner Underflow Interrupt flag is set.

Bit 10 – DFLLOVF DFLL Tuner Overflow Interrupt Enable

Writing a zero to this bit has no effect.

Writing a '1' to this bit will set the DFLL Tuner Overflow Interrupt Enable bit, which enables the DFLL Tuner Overflow interrupt.

ValueDescription
0The DFLL Tuner Overflow interrupt is disabled.
1The DFLL Tuner Overflow interrupt is enabled, and an interrupt request will be generated when the DFLL Tuner Overflow Interrupt flag is set.

Bit 9 – DFLLLOCK DFLL Lock Interrupt Enable

Writing a zero to this bit has no effect.

Writing a '1' to this bit will set the DFLL Lock Interrupt Enable bit, which enables the DFLL Lock interrupt.

ValueDescription
0The DFLL Lock interrupt is disabled.
1The DFLL Lock interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Interrupt flag is set.

Bit 8 – DFLLRDY DFLL Ready Interrupt Enable

Writing a zero to this bit has no effect.

Writing a '1' to this bit will set the DFLL Ready Interrupt Enable bit, which enables the DFLL Ready interrupt.

ValueDescription
0The DFLL Ready interrupt is disabled.
1The DFLL Ready interrupt is enabled, and an interrupt request will be generated when the DFLL Ready Interrupt flag is set.

Bit 2 – CLKFAIL XOSC Clock Failure Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a '1' to this bit will set the XOSC Clock Failure Interrupt Enable bit, which enables the XOSC Clock Failure interrupt.

ValueDescription
0The XOSC Clock Failure interrupt is disabled.
1The XOSC Clock Failure interrupt is enabled, and an interrupt request will be generated when the XOSC Clock Failure Interrupt flag is set.

Bit 1 – XOSCFAIL XOSC Startup Failure Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a '1' to this bit will set the XOSC Startup Failure Interrupt Enable bit, which enables the XOSC Startup Failure interrupt.

ValueDescription
0The XOSC Startup Failure interrupt is disabled.
1The XOSC Startup Failure interrupt is enabled, and an interrupt request will be generated when the XOSC Startup Failure Interrupt flag is set.

Bit 0 – XOSCRDY XOSC Ready Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a '1' to this bit will set the XOSC Ready Interrupt Enable bit, which enables the XOSC Ready interrupt.

ValueDescription
0The XOSC Ready interrupt is disabled.
1The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC Ready Interrupt flag is set.