29.5.1 Voltage Regulators

The main regulators output supply level is automatically defined by the Sleep mode selected in the Power Manager module.

The user LDO regulator is disabled by default, as well as the additional Regulator(s)

The LDO regulator can be enabled and disabled by writing the ULDOEN bit high in the VREGCTRL register.

The VDDCORE supplies VDDCORE_SW, VDDCORE_RAM, VDDCORE_BU, if enabled in Standby mode.

It is highly recommended to activate charge pumps when VDDA/VDDIO is too low (<2.5V). The control of Charge pump n (n = 0,1) is managed by setting the corresponding bit in VREGCTRL.CPEN[1:0]. When CPEN[n] bit is set, the enable and auto-enable modes of the charge pump[N] are set. In standby mode, the charge pumps are automatically turned OFF except if a consumer (PTC, ADC or AC) of the charge pump is requesting the charge pump.